# Welcome to Quilter

Quilter streamlines PCB design with automated PCB layout, physics checks, and iterative design tools, reducing the time from concept to production.

Welcome to Quilter's documentation.&#x20;

Here, you'll find an overview of the features and functionality that Quilter offers to help you generate, explore, and optimize fabrication-ready circuit boards in hours instead of weeks.

### Jump right in

{% content-ref url="/pages/a4o6xLdvBE0EAcuFhSbn" %}
[Quickstart](/get-started/quickstart)
{% endcontent-ref %}

### Keep exploring

#### Quilter basics

<table data-card-size="large" data-view="cards"><thead><tr><th></th><th></th><th data-hidden data-card-target data-type="content-ref"></th></tr></thead><tbody><tr><td><strong>About Quilter</strong></td><td>Learn about why Quilter exists and how it works.</td><td><a href="/pages/Zvukm7MAGL6ooitMTmpY">/pages/Zvukm7MAGL6ooitMTmpY</a></td></tr><tr><td><strong>Using Quilter</strong></td><td>Learn how to upload design files and generate layout candidates.</td><td><a href="/pages/7aUFmnCMx9m4smGncsXL">/pages/7aUFmnCMx9m4smGncsXL</a></td></tr></tbody></table>

#### Configuring design requirements

<table data-card-size="large" data-view="cards"><thead><tr><th></th><th></th><th data-hidden data-card-target data-type="content-ref"></th></tr></thead><tbody><tr><td><strong>Physics Constraints</strong></td><td>Identify your designs' key signals and concerns.</td><td><a href="/pages/JqyPuUJihRNVVnNT19bP">/pages/JqyPuUJihRNVVnNT19bP</a></td></tr><tr><td><strong>Design Parameters</strong></td><td>Constrain elements of your design.</td><td><a href="/pages/EHy5Jq3hqZ21B3Hupru6">/pages/EHy5Jq3hqZ21B3Hupru6</a></td></tr></tbody></table>

#### Reviewing layout candidates

<table data-card-size="large" data-view="cards"><thead><tr><th></th><th></th><th data-hidden data-card-target data-type="content-ref"></th></tr></thead><tbody><tr><td><strong>Reviewing Candidates</strong></td><td>Identify and download the best candidates</td><td><a href="/pages/O7KFIj3fNp7ePE1JVQFt">/pages/O7KFIj3fNp7ePE1JVQFt</a></td></tr><tr><td><strong>Physics Rule Checks (PRCs)</strong></td><td>Validate design functionality</td><td><a href="/pages/CWMdylEJnQkGi7wLROTd">/pages/CWMdylEJnQkGi7wLROTd</a></td></tr></tbody></table>


# Quickstart

A concise guide covering the essential steps to quickly prepare and upload your schematic for automatic PCB layout generation with Quilter.

In a rush? Don't like reading docs? We get it.

Here's the minimum information you need to know to submit a layout job to Quilter.

### Things you must do

1. **Start with a complete schematic.** \
   Quilter only handles layout, so we can't do this for you. You must provide a complete schematic in a supported CAD file format (currently Altium, KiCAD, Cadence Allegro, and Siemens Xpedition). For more details, see [Design your schematic](/using-quilter/design-your-schematic).<br>
2. **Generate your input board file.** \
   Once your schematic is complete, create a linked board file that includes the essential information Quilter needs to generate your layout, specifically:

   1. A valid board outline
   2. Component footprints
   3. A netlist

   \*\* If you are using **Allegro** or **Xpedition** then you'll need to download and run an exporter script to generate the IPC-2581 format. These are available on the Upload files page when you create a new Quilter job.
3. **Pre-place location-sensitive components.** \
   Quilter will automatically place and route any components that are outside the board outline, and treats pre-placed components and pre-routed copper as "locked." If your board is fully placed and routed, there's nothing for Quilter to do. For more details, see [Prepare your input board file](/using-quilter/prepare-your-input-board-file)<br>
4. **Upload your design files to Quilter.** \
   Visit <https://app.quilter.ai> to create an account and follow the in-app instructions for uploading your design files. For more details, refer to [Upload your design files](/using-quilter/upload-your-design-files).

### Things You Should Avoid

* **Do not submit a fully placed and routed board.** \
  We understand you may want to test Quilter on a previously completed design, but uploading a finished layout leaves nothing for Quilter to do.<br>
* **We cannot generate a schematic for you.** \
  Quilter only creates layouts from complete schematics. If you need assistance generating your schematic, consider using a tool like [Flux.ai](https://flux.ai), [CELUS](https://www.celus.io/), or [Circuit Mind](https://www.circuitmind.io/).

### Guides for Getting the Best Results

#### [Placement Guide](/guides/placement-guide)


# Why we're building Quilter

An overview of Quilter’s mission to streamline PCB layout through physics-driven automation, enabling engineers to rapidly explore, iterate, and optimize their designs.

Quilter was founded by [an electrical engineer](https://www.linkedin.com/in/sergiynesterenko/) with a simple goal: to help engineers save valuable time by automating circuit board layout.

### More time exploring, less time implementing

PCB layout is tedious and time-consuming. At Quilter, we envision a world where engineers spend more time exploring ideas and less time implementing them in CAD tools. A world where there are virtually no barriers or latency between documenting the requirements of a new physical product, and beginning to explore the tradeoffs and possibilities that could make it a reality.

Our vision is for Quilter to empower engineers and creators to rapidly explore ambitious ideas, understand interconnected constraints, and quickly discover optimal solutions. Quilter is purpose-built to facilitate software-driven creation and iteration, freeing engineers from the burden of manually specifying exactly how a board should be laid out.

### Physics as a north star

Most EEs know that just because a PCB design is *complete* doesn't mean it's going to *work*.&#x20;

PCB design fundamentally revolves around physics—electromagnetic behavior, current flow, thermal management, and timing constraints define a board’s success. At Quilter, we aim to anchor every layout decision in these physical realities, guiding our automated processes to generate, evaluate, and improve designs accordingly.

Because humans can't mentally simulate complex interactions like crosstalk or impedance, they often design conservatively, introducing inefficiencies such as oversized boards, unnecessary routing margins, or overly cautious constraints. Quilter combines reinforcement learning with rigorous physics-based rule checks, enabling it to push beyond human limitations to continuously optimize boards for performance, density, and manufacturability.

We're not only pursuing faster PCB layouts—we’re striving for better ones. Our goal is enable Quilter to create leaner, higher-performing boards precisely tailored to their functional requirements, eliminating manual guesswork and iterative redesigns. While Quilter is significantly faster, it is continually evolving to match and eventually surpass the optimization skills of expert human designers.

For details on our current progress and capabilities, see [What Quilter does well](/about-quilter/what-quilter-does-well).

### Iterate early & often

Ironically, it's often faster and cheaper to fabricate and ship a circuit board from halfway around the world than it is to manually design it in the first place. Slow, manual layout processes mean that failed design iterations can significantly delay R\&D timelines, causing many teams to adopt overly cautious, linear approaches that limit the ability to learn by *building*.

Quilter's objective is to transform this approach with the help of automation. By dramatically accelerating PCB layout, Quilter enables engineers to prototype immediately, iterate frequently, and rapidly refine their designs. Instead of cautiously committing to one design, teams can quickly test multiple candidates, identify issues early, rapidly adapt to real-world constraints, and evolve their solutions faster.

The result is a more agile development cycle that emphasizes rapid learning and continuous improvement. Engineers using Quilter don’t just build faster; they build smarter, gaining deeper insights into design tradeoffs, uncovering unexpected solutions, and delivering superior products to market in significantly less time.


# Why should I use Quilter?

Key reasons to adopt Quilter’s AI-powered PCB layout automation, highlighting faster time-to-market, efficient iterative design, reduced errors, and optimized use of engineering talent.

> Quilter can't design *every* PCB, but if it *can* design it, Quilter should.

We've spoken with dozens of world-class hardware design teams and have never encountered an organization where PCB layout wasn't a bottleneck. The reality is that there are far too few experienced layout engineers to meet the rapidly growing demand for PCBs.

The best organizations are experimenting with new automation and AI-powered tools to transform their cultures and become faster, more efficient, and more effective than ever. &#x20;

There are numerous reasons to start adopting AI-powered automation tools like Quilter; here are a few of the most common ones:

### Get to market faster

Quilter dramatically reduces PCB design cycle times by automating the layout process. Traditional manual layouts can take weeks, but Quilter generates optimized design candidates within hours. Accelerating your PCB design cycles enables you to get your products to market faster, seize opportunities ahead of competitors, and respond swiftly to customer feedback and emerging market demands.

### Improve designs through iteration

Quilter’s automation allows engineers to quickly and easily test multiple layout iterations, which is often impractical in manual workflows due to time constraints. With Quilter, you can rapidly explore design alternatives and trade-offs, leading to innovative solutions and higher-performing boards. More experimentation facilitates the discovery of the best design outcomes, rather than settling for the first viable option.

### Protect your best engineers

Experienced PCB layout engineers are a scarce and valuable resource. Quilter offloads tedious, repetitive tasks so your most skilled engineers can focus on challenging, high-impact design decisions that truly benefit your products. By automating mundane aspects of layout, you safeguard and maximize your team’s most valuable engineering expertise.

### Eliminate costly mistakes

Quilter’s physics-based rule checks and automated design processes significantly reduce the human error inherent in manual layouts. Every generated candidate undergoes rigorous validation to ensure compliance with real-world constraints, drastically lowering the likelihood of costly design errors and re-spins. Spending less time fixing mistakes means more resources are available for innovation and growth.

### Design and iterate faster

Leveraging AI-driven automation, Quilter provides immediate design iterations without waiting days or weeks for manual updates. By quickly generating multiple layout options, teams can iterate rapidly, test assumptions frequently, and optimize designs efficiently. This AI-driven agility ensures continuous improvement throughout the product development process.


# How does Quilter work?

An overview of Quilter’s physics-driven approach to automated PCB layout, constraint handling, and validation.

Quilter is different from all other ECAD automation solutions because:

1. **It understands good and bad physics**, eliminating the need for you to program tedious design rules to get good results
2. **It explores multiple stack-ups simultaneousl**y and customizes each candidate for the stack-up it's designing with
3. **It validates functionality with Physics Rule Checks (PRCs)** to ensure that designs are likely to function as intended.

### How Quilter is different from traditional ECAD tools

Quilter is different from automation features in an ECAD tool in a few important ways:<br>

1. **You specify constraints at the physics level, not the rules level.** \
   Most ECAD tools—even those with automation features—do not recognize the fundamental physics constraints present within a schematic. This means that humans must manually define the geometric rules needed to satisfy the physics requirements.\
   \
   Working with Quilter is closer to working with a layout engineer. Our goal is to understand the constraints at the physics level, allowing Quilter to calculate and apply the appropriate geometric constraints for every design variant (and stack-up) that it investigates.&#x20;

<img src="/files/s6BnT3Abc3K5MLftjYOn" alt="Quilter understands constraints at the physics level so it can generate correct geometric rules for each of the many stack-ups that it explores." class="gitbook-drawing">

Learn more:

{% content-ref url="/pages/JqyPuUJihRNVVnNT19bP" %}
[Physics Constraints](/physics-constraints/overview)
{% endcontent-ref %}

2. **Quilter explores many stack-ups and design candidates simultaneously.**\
   In most CAD workflows, the stack-up is one of the first design parameters that gets locked down. This means that key decisions impacting electrical performance – such as layer count, material properties, and layer assignments – must be specified before the design process begins.\
   \
   With Quilter, your company's preferred stack-ups and compatible fabrication rules are pre-loaded into the system, enabling Quilter to explore multiple candidates and recommend the stack-up that achieves the best trade-offs between speed, cost, and physics performance.&#x20;

<img src="/files/Gm9m85FBMO9sA3RYUocc" alt="Quilter can explore many candidates in parallel, letting you select the stack-up and design rules that produce the best combination of speed, cost, and performance." class="gitbook-drawing">

Learn more:

{% content-ref url="/pages/EHy5Jq3hqZ21B3Hupru6" %}
[Design Parameters](/design-parameters/overview)
{% endcontent-ref %}

3. **Quilter validates functionality with Physics Rule Checks (PRCs)**\
   Quilter provisions dedicated Physics Rule Checks (PRCs) aligned directly with the physics constraints you define in your schematic. This ensures rigorous validation directly tied to electrical performance criteria, such as impedance control, signal integrity, and thermal management.

   \
   When Quilter generates your design, it runs PRCs against each candidate layout and stack-up variation in parallel. PRCs quickly identify potential physics violations, ensuring each design iteration aligns precisely with your specified requirements. This automated validation process significantly reduces manual review efforts and enhances reliability, ensuring that each finalized PCB design consistently meets your performance goals.

Learn more:

{% content-ref url="/pages/CWMdylEJnQkGi7wLROTd" %}
[Physics Rule Checks (PRCs)](/physics-rule-checks-prcs/overview)
{% endcontent-ref %}


# What Quilter isn't

An explanation of Quilter’s role as a fully automated layout service, highlighting its workflow, scope, and limitations.

### Quilter is a design agent, not a "copilot".

Quilter is built to handle PCB layouts from start to finish on its own, while respecting your given constraints. It's not meant to augment your manual design process within existing CAD tools. If you're looking for a tool that can generate, review, apply, or discard arbitrary blocks of schematic or layout, Quilter isn't for you.

Instead, think of Quilter as a reliable and efficient junior layout engineer who's responsible for designing a portion of your team's work. They'll respond to your design feedback in an iterative and diligent way.

### Quilter is a submission and review interface, not a CAD tool.

Quilter is designed to make collaboration easy by working seamlessly with the design files from your existing CAD tools. We also return completed layouts in the same file format we receive.&#x20;

Think of Quilter's web application as a collaboration tool for coordinating design requests with external layout engineers. It's a simple way to upload, review, and exchange files and feedback with your dedicated AI designer.&#x20;

We use your CAD tool's native features whenever possible to minimize redundant data entry in Quilter. This means we rely on your tool to handle tasks like:

* Updating board files
* Modifying or annotating schematics
* Defining stack-ups and fabrication parameters
* Adjusting component positions

### Quilter is a constraint-driven workflow, not a magician.

Users often think that Quilter can look at a PDF schematic and automatically pick up on all the electrical engineering details that may or may not be included in the design.

Although that sounds great, that's not how Quilter works right now. Instead, Quilter is designed to create layouts that meet the constraints set by the input board file and during Circuit Comprehension.&#x20;

The simplest way to think about this is the following:\
**If a specific design requirement isn't specified in the input file (outline, components, placement region) or in Circuit Comprehension (see** [Physics Constraints](/physics-constraints/overview))**, Quilter will treat it like a generic signal.**

We're always working to expand our vocabulary of physics constraints and our auto-detection logic to get closer to this "magic black box" experience. But in the interim, it's important to clearly define your requirements up front to give Quilter the best chance at success.

### Quilter is an implementer, not a proofreader.

Quilter's main job is to create layouts that meet the schematic and physics constraints you provide.&#x20;

Our Physics Rule Checks (PRCs) help ensure consistency with these constraints, but Quilter doesn't check schematic logic or design intent beyond what you specify. We don't automatically review datasheets to verify that you haven't left a pin floating or forgotten to provide bypass to a power pin.

That's why it's crucial to keep applying your internal validation processes to ensure overall design correctness and functional integrity. This includes:

* Schematic reviews
* Design reviews, including running DRCs
* Signal simulation and validation
* Regular fabrication and testing<br>


# What Quilter does well

A concise summary of Quilter’s recommended applications and optimal design parameters.

Quilter can do a lot, but there are many things it can't do yet. For a complete list of supported physics constraints, see [Physics Constraints](/physics-constraints/overview).

### Recommended applications

Right now, Quilter can't typically design or optimize boards as well as skilled humans.&#x20;

Quilter's main advantage is speed—it designs boards much faster than humans, can create multiple layouts at once (for different stack-ups, fabricators, and schematic versions), and can thoroughly test whether a design will work as expected through Physics Rule Checks.

Think of Quilter as a junior EE that can support and supplement your experienced layout engineers. (see [Why should I use Quilter?](/about-quilter/why-should-i-use-quilter)). This makes Quilter well-suited to tackle the following types of designs:

#### Research & Development

* **IC Evaluation Boards:** Speed up lab testing with early hardware access
* **Design Validation:** Shorten functional validation cycles
* **Connector Breakouts & Harnesses:** Quick turnaround for signal access and subsystem testing

#### Testing & Automation

* **Test Fixtures and Harnesses:** Automate time-consuming internal board testing
* **Environmental Testing:** Create multi-channel IC test and validation boards

#### Time-Sensitive Layouts

* **Schematic-to-Test Workflow:** Skip the layout step in test board development
* **Agile Prototyping:** Iterate quickly with zero layout delay
* **Low-Complexity Designs:** Free up engineering time and avoid layout bottlenecks

### Recommended design parameters

We currently recommend Quilter for the following designs:

#### General specifications

* **<5,000 pins:** Quilter is most likely to generate successful candidates for designs with 5,000 pins or fewer.
* **Low to medium density designs:** Quilter cannot optimize designs better than humans, so very high-density designs (>20% pin density) are best handled manually.

#### High-speed digital designs

* **Signals < 6GHz:** Quilter uses quasi-static approximations to calculate design specifications for impedance-controlled signals, which may not be accurate above 6GHz.

#### **Low voltage**

* **Low-voltage designs (48V or less):** Quilter does not currently support the required physics constraints to manage dielectric breakdown, creepage and arcing for high-voltage designs. We recommend manually separating high-voltage signals before submitting them to Quilter.

#### **Low current**

* **Low-current designs (10A or less):** Quilter is not (yet) designed for very high current applications. When using high current designs, we recommend using pours to to route the net (see "attempt power pour" in the high power comprehension).&#x20;

<br>


# FAQ

### Contents

[What's the best way to evaluate Quilter?](#whats-the-best-way-to-evaluate-quilter)

[Is Quilter a copilot?](#is-quilter-a-copilot)

[How is Quilter different from an autorouter?](#how-is-quilter-different-from-an-autorouter)

[How does Quilter use AI to generate designs?](#how-does-quilter-use-ai-to-generate-designs)

[How is Quilter different from other AI design tools?](#how-is-quilter-different-from-other-ai-design-tools)

[Is it hard to learn to use Quilter?](#is-it-hard-to-learn-to-use-quilter)

[Can Quilter generate or validate schematics?](#can-quilter-generate-or-validate-schematics)

[Can Quilter manage component libraries and footprints?](#can-quilter-manage-component-libraries-and-footprints)

[Can Quilter implement reference designs from datasheets?](#can-quilter-implement-reference-designs-from-datasheets)

[How many layers can Quilter support?](#how-many-layers-can-quilter-support)

[How does Quilter handle reference designators?](#how-does-quilter-handle-reference-designators)

[Do I have to enter physics constraints manually?](#do-i-have-to-enter-physics-constraints-manually)

[Does Quilter train on my designs?](#does-quilter-train-on-my-designs)

[Do you support on-premise deployments?](#do-you-support-on-premise-deployments)

[Where is Quilter's team located?](#where-is-quilters-team-located)

[How can I delete my account?](#how-can-i-delete-my-account)

[Adding or removing team members](#adding-or-removing-team-members)

[How can I monitor my enterprise team's usage?](#how-can-i-monitor-my-enterprise-teams-usage)

### What’s the best way to evaluate Quilter?

The best way to evaluate Quilter is by starting with a known-good design you’ve previously completed. By submitting your existing schematic and board files, you can quickly compare Quilter’s output to your original layout, clearly benchmarking improvements in layout speed, manufacturability, and quality.

\
Quilter offers both a free version and an enterprise version, each designed to meet different user needs. The free version allows users to explore its core functionalities, while the enterprise version includes advanced features such as a commercial license and enhanced data privacy measures.\
With this approach, you can easily validate Quilter’s capabilities and see firsthand the time savings and layout improvements it provides. Quilter also offers free evaluation support and customized evaluation programs for enterprise customers to ensure a seamless and productive experience.<br>

The enterprise version offers additional benefits, including a commercial license for intellectual property generated using Quilter and enhanced data privacy, ensuring that uploaded designs are not used for training data.<br>

**To start your evaluation, you can either:**

* Create a Non-Commercial Account to evaluate the free version by submitting designs to our multi-tenant application at [https://app.quilter.ai](https://app.quilter.ai/)
* [Request a Demo](https://www.quilter.ai/demo) to explore the enterprise version and access support through our White Glove Evaluation Program.

### Is Quilter a copilot?

No — Quilter is not a copilot in the traditional sense. While many tools aim to assist human designers and incrementally improve their efficiency, Quilter is built for full automation. It doesn’t require a layout engineer to manually guide or interact with it during the design process.

Instead of serving as a productivity booster for your top layout engineers, Quilter generates complete board layouts on its own, freeing up human resources for tasks like system-level architecture or design for manufacturing. This makes it especially valuable in R\&D environments where quick iteration on low-volume boards is essential and layout resources are limited.

That said, we understand that no model is perfect. When needed, Quilter offers mechanisms to review and modify its output, but its main goal is to eliminate the need for manual layout from the start.

### How is Quilter different from an autorouter?

Quilter is more than just an autorouter — it’s a complete PCB layout engine. Unlike traditional autorouters, such as the one in Altium, which only focus on routing traces and often require manual cleanup for complex designs, Quilter handles the entire layout process. This includes placement, selecting stack-ups, defining pour strategies, and checking constraints based on physical properties— all seamlessly integrated into the workflow.

Instead of making you micromanage things like widths, separations, and impedance rules, Quilter asks for a higher-level understanding (like “this net is 50Ω impedance-controlled”) and takes care of the rest automatically. This leads to more accurate, manufacturable designs — especially for complex, high-pin-count boards like DDR4 memory systems.

Most importantly, we strive for 100% completion. Autorouters often give up around 70–90%, leaving designers to sort out messy, unusable partial results. With Quilter, a design that doesn’t fully route is considered a failure. That focus on full automation, combined with physics-aware layout and rapid product evolution, sets Quilter apart.

### How does Quilter use AI to generate designs?

Quilter uses a physics-driven AI approach called reinforcement learning to create PCB layouts — similar to how AlphaGo learned to play Go by playing against itself repeatedly. Instead of relying on human-designed boards as examples, Quilter explores numerous layout possibilities on its own, evaluating each with detailed physics assessments we call Physics Rule Checks (PRCs).

Over time, this self-guided approach lets Quilter continuously improve and adapt, optimizing designs based on real-world physics considerations like thermal management, EMI, impedance control, and more. Right now, our focus is on quickly generating designs for rapid real-world testing, and we’ll keep expanding the complexity and depth of physics feedback built directly into Quilter’s automated layout process.

### How is Quilter different from other AI design tools?

Quilter uniquely integrates with your existing tools and delivers full PCB layout automation using physics-driven reinforcement learning. Quilter sets itself apart from other AI-driven ECAD tools with three key advantages: seamless integration, a sole focus on layout automation, and integrated physics modeling.

First, Quilter integrates smoothly with your existing design tools, so you don’t have to switch software or disrupt your workflow to use its capabilities.

Second, Quilter focuses exclusively on PCB layout automation, whereas most competing tools prioritize automating or streamlining schematic capture. Quilter tackles the challenges of component placement, impedance control, routing, and design-rule validation head-on.

Lastly, unlike other AI approaches that learn by mimicking human-designed boards, Quilter uses physics-based reinforcement learning. It autonomously generates and evaluates layouts through detailed physics simulations, ensuring each design is optimized according to fundamental electrical and manufacturing principles, not just replicating previous human-created patterns.

### Is it hard to learn to use Quilter?

Engineers typically submit their first design in Quilter within minutes, making it quick and easy to learn. Quilter doesn't offer a full CAD interface, but rather replicates the conversation between an electrical engineer and a layout engineer when starting a new design.

It's designed to be intuitive and easy to use, with a super short learning curve. Most engineers submit their first design within 5–10 minutes of signing up. The intuitive interface and automated processes mean you don’t need extensive training to get started.

As you use Quilter, you’ll quickly get familiar with its capabilities and configurations. Typically, engineers become proficient after just a few submissions, rapidly iterating to refine layouts and optimize results.

### Can Quilter generate or validate schematics?

No — Quilter does not generate or verify schematics. It exclusively focuses on automating the PCB layout process. Quilter assumes the schematic you provide is correct, using it as the starting point for layout generation.

By automating layout tasks, Quilter significantly reduces the time needed to produce prototypes, allowing your team to quickly identify schematic issues through real-world testing and iterations. However, schematic validation and creation remain outside Quilter’s current scope.

### Can Quilter manage component libraries and footprints?

Quilter doesn't manage or create component libraries and footprints itself. Instead, it relies on the libraries and footprints you already have in your current ECAD tools. When you upload your schematic and board files, Quilter keeps and uses the footprints exactly as you defined them.

This approach ensures consistent, trusted component definitions and reduces the risk of component mismatch or errors in your designs. Quilter focuses on placement and routing, leaving you in full control of your library standards and component quality.

### Can Quilter implement reference designs from datasheets?

Quilter does not directly import or automatically implement reference designs from component datasheets. However, you can manually place and route critical reference layouts — such as switching regulators or RF circuits — exactly as specified by the datasheet, and Quilter will fully respect and preserve your layout decisions.

Any manual placements or routing you provide remain untouched during Quilter’s automated layout process. Quilter then completes the rest of the design around your predefined reference areas, seamlessly integrating your precise manual implementations with automated routing.

### How many layers can Quilter support?

Quilter currently supports a range of PCB layouts, from basic 2-layer designs to complex multilayer stack-ups with 10 layers or more. In reality, adding extra layers often simplifies automated layout for Quilter, as they provide more space for routing and power planes.

There's no fixed upper limit — Quilter can handle extremely complex multilayer stack-ups defined in your manufacturing profile, giving you the flexibility to meet a wide variety of design needs.

### How does Quilter handle reference designators?

Quilter does not currently handle or optimize silkscreen placement. While component placements include associated silkscreen outlines, Quilter does not automatically resolve silkscreen overlaps or positioning issues.

When Quilter places components, it maintains the same relative position of the silkscreen reference designators, which can sometimes lead to silkscreen collisions.

After Quilter generates the PCB layout, you may need to manually adjust silkscreen markings within your ECAD tool to ensure readability, compliance, and manufacturability. Improved silkscreen handling is planned for future updates but isn’t available today.

### Do I have to enter physics constraints manually?

No — Quilter automatically detects and extracts key physics constraints directly from your schematic. It identifies constraints such as impedance-controlled signals, differential pairs, length matching, high-current nets, and sensitive circuits through its Circuit Comprehension interface.

After Quilter extracts these constraints, you review and verify them for accuracy. You can manually adjust or add additional constraints if needed, ensuring the layout meets your precise design requirements.

### Does Quilter train on my designs?

No — Quilter does not train on any **paying customer** designs or human-created layouts. We never collect or use **paying customer** data to train or improve our models. Your schematic and constraints are used only to generate your board layout, and once the job is complete, that data is discarded from the training process.

Instead of learning from human examples, Quilter primarily uses a self-play approach similar to AlphaGo. The system explores many layout possibilities on its own and evaluates them with physics simulations to learn from the outcomes. This method allows us to avoid the limitations of human-designed training data and scale learning through simulation, not customer input.

This is both a core privacy promise and a technical strategy—your IP remains private, and Quilter’s performance continues to improve without relying on customer-submitted designs.

{% hint style="info" %}
Training policy for our Non-Commercial (Free) Tier:\
Keep in mind that our Terms of Use for Quilter's Non-Commercial Tier, which is free for our users, permit training on both users' direct inputs and synthetic training data generated from those inputs.

For more information on the Non-Commercial Tier Terms of Use, visit [quilter.ai/terms](https://quilter.ai/terms)
{% endhint %}

### Do you support on-premise deployments?

Yes — Quilter supports multiple deployment options, including fully on-premise setups. You can choose to deploy Quilter:

* In our standard hosted cloud environment.
* Through an isolated hosted deployment on AWS or GovCloud.
* Directly on-premise within your private cloud infrastructure.

For organizations with strict IP protection needs — such as aerospace, defense (e.g., ITAR compliance), or highly secretive consumer electronics firms — deploying Quilter on-premise ensures your design data stays within your secure network.

We suggest initially testing Quilter with non-sensitive designs using our hosted environments to simplify the setup. When required, an on-premise installation is fully supported and can be easily deployed on your existing Kubernetes or private cloud environment.

#### What are the infrastructure requirements to host Quilter on-premise?

Quilter deploys into your own Kubernetes cluster as a Helm chart. The platform creates compute jobs for component placement and trace routing, scaling resource usage based on board complexity and desired throughput.

To run Quilter self-hosted, you'll need a Kubernetes cluster with access to GPU and general-purpose CPU capacity. GPU nodes should provide modern NVIDIA GPUs with at least 16 GB VRAM. CPU and GPU requirements scale with workload — fewer resources mean longer processing times, but the platform adapts to your available capacity.

Updates and upgrades are delivered as new Helm chart versions, deployed into your cluster on your own schedule.

### Where is Quilter's team located?

Our team is distributed across the United States, with significant presence in California (including Los Angeles and the Bay Area) as well as other regions nationwide.

Our team includes experts across multiple disciplines:

* Electrical Engineering: Engineers with deep expertise in PCB design and industry-leading ECAD tools.
* AI & Machine Learning: Specialists focused on applying reinforcement learning and simulation-driven methods to PCB layout automation.
* Computational Geometry: Experts skilled in geometric optimization algorithms essential for creating efficient, manufacturable layouts.

This diverse expertise allows Quilter to provide innovative automation solutions that blend industry best practices with advanced computational techniques.

### How can I delete my account?

We understand you may need to delete your account and data. Whether you are no longer using our services or simply want to start fresh, we want to make the process as easy as possible for you.

1. Send Us an Email\
   To start deleting your Quilter account and data, please email our team at <team@quilter.ai>. Make sure the email you send matches the one you used to sign up for Quilter. After we receive your email, our team will begin the process of permanently deleting your account and all related data.\
   ​
2. Confirm deletion\
   Once we receive your email, we'll send a confirmation email to verify that you're the account owner and that you want to delete it. Please reply within 24 hours to confirm the deletion. If we don't hear back from you within 24 hours, we'll assume you no longer want to delete your account, and the process will be cancelled.\
   ​
3. Account and Data Deletion\
   After we receive your confirmation, our team will go ahead with deleting your Quilter account and all related data. This process can take up to 7 business days to finish.

#### Account deletion is permanent!

Please note that once your account and data have been deleted, they cannot be recovered. This includes all saved layout jobs, generated layouts, and any other information associated with your account.

### Adding or removing team members

You can easily manage the individuals who have access to your Quilter license by adding or removing team members. Here’s how:

#### Requesting Team Changes

To add or remove someone from your Quilter license, simply reach out to us at <support@quilter.ai> or submit a support ticket through our chat bubble. Please make sure to include:

* The email address of the person you want to add or remove.
* Specify clearly if you’re requesting an addition or a removal.
* If you want to remove an account, please specify whether you would like to:
  * remove it from the team's license without deleting it,
  * suspend it to prevent user access without deleting data, or
  * delete it entirely, including all Input Data, layout jobs, and submitted candidates.

{% hint style="info" %}
Note: Accounts removed from an active enterprise license but not suspended will be downgraded to our Non-Commercial Tier. The user will be unable to submit new layout jobs until they accept the latest Terms of Use.
{% endhint %}

#### Adding New Team Members

When adding a new member, our team will:

* Send an invitation email to the new user, prompting them to join your Quilter organization.
* If they already have a Quilter account, we’ll link their existing account directly to your team license.
* Ensure their account is properly configured with access permissions associated with your organization’s Quilter license.
* Enable easy monitoring of their usage through your team’s dashboard.

#### Removing Existing Team Members

When removing a member from your team, we will:

* Securely deactivate or revoke their access to your team’s Quilter license.
* Confirm the removal to ensure your organization’s security and account integrity are maintained.

If you have any questions or need further assistance with team management, please reach out to our support team.

### How can I monitor my enterprise team's usage?

Quilter's Usage Dashboard is a helpful tool that allows you to easily track your team's usage and see how it compares to your annual commitments.&#x20;

The Usage Dashboard can help you answer common questions about your Quilter usage, such as:

* How many pins total has my team used?
* How many pins did we use this week / this month?
* Are we on track to meet our annual commitments?
* Who's using Quilter the most?
* How many pin credits did my layout job consume?

<figure><img src="/files/PjS8LeD24N0d5OxTAtdI" alt="" width="563"><figcaption></figcaption></figure>

*Note that our usage dashboard is not real time, and data may be delayed by as much as 1-2 hours.*

**Accessing the Dashboard**\
The Usage Dashboard can be accessed by clicking on the help bubble in the bottom right corner of your screen and selecting the 📊 View and explore billable usage button.

If this is your first time using the dashboard, you may need to create a separate account. Please note that this account is managed separately from your Quilter account.

#### Dashboard Views

The dashboard offers three primary views to help you understand your usage:

**Usage Summary**\
The Usage Summary provides an overview of all billable usage for your Quilter PO. This includes your contracted commitments, pin downloads per month, and pin downloads by users.

**Usage Detail (by User)**\
The Usage Detail (by User) view provides a breakdown of billable and non-billable activity for all users with access to your Quilter PO. This can help you identify which users are utilizing Quilter the most.​

**Usage Detail (by Month)**\
The Usage Detail (by Month) view summarizes billable and non-billable usage activity by month. This can help you track your usage over time and identify any trends.

**Contacting Support**\
If you have any questions about your usage or need assistance with the Usage Dashboard, you can click the "Contact Support" button at the top of the page or send an email to <support@quilter.ai>. Our support team will be happy to assist you.


# Placement Guide

Getting the best results out of Quilter's Placement Engine

## Placement control

There are several ways you can indicate your component placement intents to the Placement Engine. The more specific you are, the less freedom Quilter has to move components around and possibly get a better routing result. The sections below detail the different ways you can control the Placement Engine, ordered from most freedom/least restriction to zero Quilter freedom on manual placements.

{% hint style="info" %}
If you leave vias on the board, Quilter assumes they are intentional and they will block component placements!
{% endhint %}

[Learn how to make Rooms or Regions in your ECAD tool](/design-parameters/placement-regions#as-a-requirement)

### Ways to control Placement, ordered from fully Quilter to fully human

### 1. Schematics-based clustering

<figure><img src="/files/KeDVnR0hyT3YKEzDrHIl" alt="" width="375"><figcaption></figcaption></figure>

Quilter interprets explicit wire connections between components in the schematic, and attempts to place those components close together. This way the organization scheme of your schematic is represented on the board. These groups won’t have a predetermined location on the board, and will move based on the requirements of other groups.

### 2. Anchoring

If you preplace one or more components of a group within the board outline, all the other components from that group will “stick” to it. You could place a connector on the board, and if it has explicit wires in the schematic to various protection or decoupling components, they’ll automatically be placed close to the connector. Similarly you could place an IC where you’d like it to be on the board, and not worry about manually placing the passives that support it—Quilter will take care of placing them as closely together as possible.

### 3. Placement regions

Placement regions (or rooms) are a powerful tool for expressing more precise control over Quilter’s placer logic They’re especially useful when you have groups of components that need to be placed close together or far apart, like analog and digital circuits and switching converters.

Placement regions can be placed on the board in your ECAD tool or left outside the board outline, and Quilter will interpret these differently.

#### 3a. Region outside of board area

<figure><img src="/files/A6lQabsfHUCB27hC1zoD" alt="" width="375"><figcaption></figcaption></figure>

If the region is left off of the board, Quilter will consider any components in the region as part of a group. This works similarly to the schematics-based clustering above, and the components will be placed closely together in a location of Quilter’s choosing. You can also anchor the group by placing one or more of the components from the region onto the board.&#x20;

**The shape and size an off-board region will be ignored!** So you don't need to worry about adjusting it.

**Off-Board regions** also do not have a **side**, so components in a region that is not on the board **can be placed on the top OR the bottom** of the board.

There are a couple of advantages to this approach. First, it’s quick to apply blanket directives on your schematic to group the components, so you can manually enforce grouping behavior. Second, you save the time of planning and placing those regions on the board. Third, this light touch still allows Quilter the space to make optimization and tradeoff choices.

#### 3b. :star: Region outside the board with an anchor component placed :star:

Our current favorite. If you keep the region off the board but manually place a component or two *on* the board to anchor the group, the rest of the components will be anchored to the ones you placed.  \
\
This approach allows you to get most of the advantages of **3a**, namely the speed of setup and grouping placement, but adds in the location control of **3c** without overly constraining Quilter or adding manual region placement work.

#### 3c. Region inside of board area (or overlapping edge)

<figure><img src="/files/mXe9fybP688cjyCHSrhX" alt="" width="375"><figcaption></figcaption></figure>

This is the standard approach to using rooms or regions. You create them on the board, and components that are outside of them (after Quilter’s placement) cause DRC violations. Quilter will make a best effort to fit all the components and their required clearances within the region, though it may fail if the region is too small or the clearances are too large.

Tightly controlling the location like this is important for considerations that Quilter may not have, like components that need to be close together but for which there is no Comprehension. It’s also useful for keeping noisy components like switching converters further away.

Quilter supports **placement regions with multiple polygons** or outlines. To use this, add the same components to both rooms/regions and t**hey will be treated as a union**; the combined area of the regions. The main usage for these multipolygon regions is creating **two-sided regions**, where the polygons have the same shape but there’s one on the top layer and another on the bottom layer.

**Region Ground Pours**&#x20;

If your design has multiple ground nets and requires galvanic isolation, there will soon be an option to generate a ground pour with the same footprint as the placement region that contains the pins that connect to it. This option will be chosen in the new Ground Nets section of the Comprehensions.

### 4. Manual placement

Some components must be in a specific location, like connectors and chips with heat sinks that must align with external mechanical features. Simply place them within the board outline and Quilter will consider them “preplaced” and won’t move them. This is the most tightly specified option.


# Introduction

An overview of Quilter’s automated PCB layout service, detailing workflow steps, integration with existing CAD tools, and evaluation criteria.

Quilter is an automated PCB design software service that leverages generative AI and physics-based optimization to automate and streamline circuit board layout.&#x20;

Here's how it works:

### The basics

1. **Quilter handles the entire PCB design process from start to finish.** \
   Quilter supports the full design workflow, which includes component placement, routing, and thorough design validation through automated DRC checks and physics simulations.<br>
2. **Quilter integrates seamlessly with your current CAD tools.** \
   It works directly with both new and existing design files created within your existing CAD tools. This means you can skip using SPECCTRA, ODB, or third-party file converters. Quilter reads and writes to your design files just like your layout engineers do.<br>
3. **Whatever you start, Quilter will finish.**\
   Quilter works by placing and routing any components left outside your board outline to design your PCB to 100%. This means that you can place or route sensitive components or signals before submitting to Quilter, and it will try to complete the design for you.&#x20;

### How Quilter evaluates layout candidates

There are three key factors that Quilter considers when generating and recommending layout candidates:<br>

1. **Completeness**\
   We measure "routing completion" for each candidate as the percentage of unrouted pins that have been successfully implemented. Quilter's objective is to place and route all designs to 100%.
2. **Manufacturability**\
   Quilter's objective is to design using fabrication rules that are fully supported by the specified fabricator, and contain 0 DRC violations.
3. **Physics**\
   Quilter uses our "Physics Rule Checks" (PRCs) framework to ensure that the sensitive signals and physics constraints you specified during Circuit Comprehension are properly implemented and likely to function as expected.<br>

### Quilter's design workflow

Quilter simplifies the PCB design process into clear, straightforward steps: prepare your inputs, define your circuit comprehensions and parameters, review generated design candidates, and download your final layouts for fabrication.

{% stepper %}
{% step %}

#### [Prepare your input board file](/using-quilter/prepare-your-input-board-file)

Quilter requires a schematic and "starter" board file that includes a valid board outline, netlist, and component footprints. Leave the components you want Quilter to place and route outside of the board outline.
{% endstep %}

{% step %}

#### [Upload your design files](/using-quilter/upload-your-design-files)

Upload your design files to Quilter's web application. We will parse your board file to ensure we can correctly read your board objects, and process your schematic to automatically detect physics constraints.
{% endstep %}

{% step %}

#### [Select your stackup](/using-quilter/select-your-stackup)

Provide Quilter with details about your layout preferences, such as your desired fabricator, the number of layers, and the fabrication tolerances.&#x20;
{% endstep %}

{% step %}

#### [Define physics comprehensions](/using-quilter/define-physics-comprehensions)

Review, validate, and add or remove physics constraints in a step known as Circuit Comprehension. Quilter utilizes this information to ensure that sensitive design features are implemented correctly and to provide corresponding Physics Rule Checks that evaluate and recommend layouts.
{% endstep %}

{% step %}

#### [Submit your layout job](/using-quilter/submit-your-layout-job)

Submit your job! Quilter will explore hundreds of individual design variations with different stack-ups and fabrication tolerances, validating Physics Rule Checks (PRCs) for every constraint specified in Circuit Comprehension.
{% endstep %}

{% step %}

#### [Review layout candidates](/using-quilter/review-layout-candidates)

Review the recommended layout candidates from Quilter and choose your preferred option. Download your chosen candidate back into your original CAD file format for a final review.
{% endstep %}
{% endstepper %}

### Quilter's technical submission review process

The steps outlined here are the current actions required to prepare a board for Quilter and a guide to successful submission to Quilter. <br>

1. Open Schematic to check the following:
   1. Logical Complete Circuits on Each Schematic Page
   2. Net Class Definitions
   3. Bypass Cap ID - Explicit Assignment
2. Open board file
   1. Import changes from schematic into board file.
   2. DRC Rules Review/Run
   3. Draw Rooms/Manage Floor Plan
3. Upload to Quilter
   1. Manufacturing Guidelines
      1. Confirm Stackup/Layers Perferred
      2. Trace and Space Guidance
      3. CM and EMS Specs/Templates
   2. Physics Checks
      1. Verify Bypass Capacitors - validate
      2. Verify Differential Pair&#x20;
      3. Verify Crystals
      4. Power Nets - add by net class, discuss power pours
      5. Net Widths - are there specific widths
      6. Impedance Control - add by net class
      7. Verify Switching Converters
      8. Verify Rooms
      9. Discuss Preserve Pours
4. Submit and Run.


# Design your schematic

Concise guidelines for preparing schematics compatible with Quilter, including supported CAD platforms and design best practices.

Quilter's primary function is to design PCBs from your existing schematic. So, **before you can ask Quilter to generate your PCB, you need to have already designed your schematic.**&#x20;

Here are a few things to know when designing your schematic:<br>

1. **Supported CAD platforms:**  \
   Quilter is currently compatible with Altium, KiCAD, Cadence Allegro, and Siemens Xpedition. <br>
2. **Use native object classes whenever possible:**  \
   Whenever possible, use supported object classes to help identify important signals such as power nets, differential pairs, and important net classes. This will facilitate Quilter's automatic detection of these constraints during Circuit Comprehension.<br>
3. **Validate your design before submitting:**  \
   Quilter's objective is to faithfully represent the schematic that you provide; we do not automatically verify that your design is free from errors. Before submitting to Quilter, be sure to review your schematic as if you were designing the layout yourself.

{% hint style="warning" %}
**Multi-channel designs**\
Quilter can parse hierarchical schematics, but currently does not support symmetrical layout for multi-channel designs.
{% endhint %}


# Prepare your input board file

Instructions for creating an input board file for Quilter, covering required elements, recommended constraints, and optional parameters.

The input board file is the most crucial input to Quilter, defining the degrees of freedom that it can explore when completing your layout job.

Quilter comprehends the existing layout objects in your PCB files, including stack-ups, design rules, keepouts, pours, component footprints, and more. All design elements within the user-defined board outline (pre-placed components, routed traces, copper pours, rooms, etc.) can be designated as fixed constraints and will not be modified by Quilter during layout.

You can find more information on each of the design parameters described below in the  [Design Parameters](/design-parameters/overview) section of our documentation.<br>

### Required design parameters

Here are the required design parameters for all layout jobs. Make sure to include them in the board file you upload to Quilter:<br>

* **Board Outline**\
  You need to define a single valid board outline for Quilter to work with. Currently, Quilter can't define or resize the board outline for you, so you must do it yourself. To ensure Quilter recognizes the outline, define it on a specific layer:<br>
  * In **Altium,** use **Mechanical Layer 1 (Mechanical 1)**
  * In **KiCAD**, use the **Edge.cuts** layer

{% hint style="info" %}
Quilter only supports one closed board outline. Components with keepouts or other polygon zones defined on the same layer as the board outline can confuse Quilter's parser.
{% endhint %}

* **Component Footprints**\
  Quilter doesn't manage your component footprints, so you need to pre-load them into your board file before submitting. Quilter can't automatically try or choose from multiple footprints or packages for the same component.
* **Netlist**\
  Lastly, Quilter requires a valid netlist that matches the uploaded schematic. For the best results, please ensure your netlist is up to date with the latest version of your schematic. <br>

### Recommended design parameters

Here are some design parameters that aren't strictly required, but are recommended for most layout jobs:<br>

* **Ground and power layer names**\
  Quilter requires that ground layers be named "ground" or "gnd", and power be named "power" or "pwr" if you want those to be detected and used
* **Pre-placing components (like connectors)**\
  Quilter won't move any components you pre-place within the board outline, and will automatically route the rest.&#x20;

{% hint style="warning" %}
Quilter can't automatically distinguish connectors from other unplaced components, we strongly recommend pre-placing them to prevent your USB connector from ending up in the center of your board.
{% endhint %}

* **Not-yet-supported physics constraints**\
  Quilter can't handle all physics constraints in all designs yet. If your physics constraint isn't listed in Circuit Comprehension, Quilter won't give it special attention and will route it like a generic low-voltage, low-speed signal. \
  \
  For this reason, we recommend pre-placing and pre-routing any sensitive design elements that Quilter doesn't support yet (like trace antennas or high-speed signals over 6GHz).<br>

### Optional design parameters

* **Keepouts**\
  You can define placement or routing keepouts that Quilter will respect during the design generation process. Read more in [Keepouts](/design-parameters/keepouts).
* **Copper pours**\
  Quilter can preserve and utilize pre-defined pours for external (currently supported) and internal (coming soon) copper layers. Read more in [Preserved pours](/design-parameters/preserved-pours).
* **Placement regions**\
  Quilter supports the use of placement regions ("Rooms" in Altium) to constrain component placement. Read more in [Placement regions](/design-parameters/placement-regions).

### Stackups from input files

* **Custom stackups**\
  You can specify custom stackups in your ECAD files that Quilter will use when generating candidates. Read more in [Stackups](/design-parameters/stackups).
* **Design rules**\
  You can also specify custom fabrication rules in your input file that Quilter will use when generating candidates. Read more in [Fabricator constraints](/using-quilter/fabricator-constraints).<br>

{% hint style="info" %}
The fewer design parameters you lock down within your input file, the more flexibility you allow Quilter to explore. If Quilter fails to generate a fully complete candidate for your layout job, try relaxing design parameters in your input board file.
{% endhint %}

### Exporting files from Cadence Allegro

Download the script from the Upload files page, unzip, and follow instructions in the README.md file. These instructions are constantly updated as the script is updated.

<figure><img src="/files/tfWwZHLBDz9xvrIsPZpU" alt="" width="563"><figcaption></figcaption></figure>

### Exporting files from Siemens Xpedition

Download the script from the Upload files page, unzip, and follow instructions in the README.md file. These instructions are constantly updated as the script is updated.

<figure><img src="/files/tNmnaymRLANgrwjqQGmN" alt="" width="563"><figcaption></figcaption></figure>

Video walkthrough of using the script:

{% embed url="<https://vimeo.com/1161571386/d388f843eb>" %}


# Start a project

Instructions for using Quilter Projects

Quilter organizes jobs of similar designs into collections called Projects. As you iterate on your board design by submitting, downloading, refining, and resubmitting jobs, Projects helps keep those jobs together. Projects are also the primary way that usage is metered for enterprise customers who are billed by the board project, not by the job.

### Create the Project

For now, all you need to do is name it!

<figure><img src="/files/0qKJsT5a1v2UMymq6iid" alt=""><figcaption></figcaption></figure>

### Set up the first job in the Project

The first job you upload sets the baseline of the board project.

#### Job Similarity Requirement

Additional jobs added to the project must be within 10% variation of the pin count, component count, footprints, and component BOM of the first baseline job in a project. If you think a job is being incorrectly rejected for being too dissimilar, just ask us for help. You can iterate an unlimited number of times within a project.

#### Adding Jobs to an Existing Project

To add jobs to an existing project, open the project and click the new job button. You can also duplicate jobs within a project by selecting the action in the projects table.

### **Other things to know about Projects**

#### Project Visibility In Organizations

Enterprise customers who are part of an organization see a listing of all projects belonging to the organization in the project list. Users can create jobs in any project belonging to the organization.

#### How to Find Old Jobs Not Part of a Project

Going forward jobs must always be part of a project. To view jobs that were created in the past prior to the implementation of projects, you can click the "View All Jobs" button on the application home. This shows all jobs, both ones part of a project, and older jobs not associated with a project.

#### Project Expiration

Projects have an expiration date that depends on if you are a free or paid customer with us. Once a project expires, no new jobs can be created inside the project, though you will still be able to access the job (for how long again depends on your agreement with Quilter).


# Upload your design files

Instructions for uploading schematic, board, and project files to Quilter, including supported file formats, parsing validation, and file replacement procedures.

Quilter leverages your schematic, board, and project files to collaborate with you and design the ideal PCB layout.

### Upload your design files

Once you've created a new job, you'll be asked to upload your input files for Quilter to parse.

<figure><img src="/files/zy0FAnySUUALaIUpFJSm" alt=""><figcaption></figcaption></figure>

{% hint style="info" %}
**Only upload .zip files for Xpedition**

Quilter does not currently support uploading .zip files or nested directories, except for Xpedition
{% endhint %}

### Supported input files

[Preparing files from Cadence Allegro](/using-quilter/prepare-your-input-board-file#exporting-files-from-allegro)

[Preparing files from Siemens Xpedition](/using-quilter/prepare-your-input-board-file#exporting-files-from-siemens-xpedition)

#### Board files

**Board files define fixed design parameters.** \
Every layout job needs a "starter" board file that Quilter uses as a starting point for design exploration. This file is a required input that locks in the parameters of your layout and sets the boundaries for Quilter's exploration.\
\
Once Quilter finishes your layout job, it returns all completed designs in the same file format in which it received them. After downloading your design, you can open it directly in your CAD tool for further review.

#### **Schematics**

**Quilter uses schematics to automatically detect physics constraints.** \
With your schematic, Quilter identifies key signals and physics constraints within your design.\
\
Schematics also provide more context on how parts on the same net are connected, which helps Quilter inform component placement for groups and physics constraints for components like bypass capacitors, crystals, and switching regulators.

#### **Project files**

**Project files offer extra details** \
Project files aren't required, but they give Quilter more context about your project, which helps it accurately process complex schematics, DRC rules, and other information. They also make sure your schematic and Quilter-generated board files stay in sync after downloading layout candidates.

### Previewing input files

Once you've successfully uploaded, you'll see the following:

* The results of file parsing, including any errors
* A preview of your input board file
* A summary of your job details, such as the number of components and pins for Quilter to route within your design

<figure><img src="/files/2GIPfzo3dziadxKMpMta" alt=""><figcaption><p>File preview page</p></figcaption></figure>

Once you're confident that Quilter has processed your design files correctly, you can proceed.

### Replacing input files

If you run into a blocking error and need to upload new design files, click the "Replace Files" button in the bottom navigation bar. You'll be asked to upload new design files, and you'll need to re-upload all design files at once - not just the ones you want to replace.

{% hint style="warning" %}
**Replacing files keeps existing (valid) constraints intact**\
When you replace files, Quilter tries to keep all valid physics constraints from your previous design files. If you want Quilter to create new constraints for your updated design files, start with a new layout job from scratch.
{% endhint %}


# Select your stackup

Explanation of stackup options in Quilter.

The next step in the submission process is to choose whether to use the stackup defined in your ECAD tool or one provided by Quilter for a known fabricator.

<figure><img src="/files/jhH8ez3PiOkMwBEyYJJk" alt=""><figcaption></figcaption></figure>

You can find a more detailed discussion of [Stackups](/design-parameters/stackups) in that section


# Fabricator constraints

Overview of Quilter’s fabrication rules, detailing how they define geometric constraints for manufacturability and ensure compliance with fabricator capabilities.

### Overview

Fabricator constraints are a subset of the overall constraints that define the minimum geometric thresholds a fabricator can apply when manufacturing your circuit board.&#x20;

Specifically, Quilter's fabrication rule profiles include the following:

* Minimum trace width
* Minimum trace clearance
* Minimum drill hole size
* Minimum annular ring size
* Minimum edge-to-copper clearance

### How Quilter uses fabrication rules

These are the **absolute minimums** that your fabricator will allow. Any smaller dimension defined later, including by specifying a netwidth, will be ignored or will generate a DRC violation.

### How to specify

If using your own stackup, these will be read from your ECAD files. When using a Quilter stackup, these will be part of that definition.

In the Quilter app, you can double click a value to edit it.


# Define physics comprehensions

An overview of Quilter’s Circuit Comprehension step, outlining how to define and validate physics constraints for your PCB layout.

Next up in Quilter's submission process is Circuit Comprehension. This step aims to give Quilter insight into the main physics concerns associated with your design.&#x20;

<figure><img src="/files/SlqMZK0jROHIlqbupt5O" alt=""><figcaption></figcaption></figure>

Quilter tries to automatically detect as many constraints as possible by analyzing object classes in your input files and inferring constraints from your project netlist. However, some constraints need to be manually defined.&#x20;

Refer to the tables below for a summary of the physics constraints supported by Quilter.

{% hint style="warning" %}
Quilter treats all signals **not** represented in Circuit Comprehension as generic, low-speed digital signals. If your physics constraints are not yet supported by Quilter, we recommend pre-placing or pre-routing them before submission.&#x20;
{% endhint %}

### Routing constraints

<table><thead><tr><th width="200.10791015625">Constraint</th><th width="399.79052734375">Details</th><th>Automatic?</th></tr></thead><tbody><tr><td><a data-mention href="/pages/6n6pBLMX9LH3mW3zGWDT">/pages/6n6pBLMX9LH3mW3zGWDT</a></td><td>Design high-current nets as traces with a specified width or as copper pours.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/FQkEcqQF14sKwWxhqUWU">/pages/FQkEcqQF14sKwWxhqUWU</a></td><td>Generate differential pairs with controlled lengths and impedances for high-speed digital signals.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/PYz2sZ6jr6LwiNiNHOhF">/pages/PYz2sZ6jr6LwiNiNHOhF</a></td><td>Impedance-controlled nets for RF nets or other fast, long, or sensitive traces.</td><td>Manual</td></tr><tr><td><a data-mention href="/pages/AWyphmkmhKFzQOw9o2MC">/pages/AWyphmkmhKFzQOw9o2MC</a> (coming soon)</td><td>Length matching for timing-sensitive interfaces such as DDR memory</td><td>Manual</td></tr></tbody></table>

### Placement constraints

<table><thead><tr><th width="199.79901123046875">Constraint</th><th width="400.1043701171875">Details</th><th>Automatic?</th></tr></thead><tbody><tr><td><a data-mention href="/pages/UoFdbNAFEuvp1pOFyMPf">/pages/UoFdbNAFEuvp1pOFyMPf</a></td><td>Position oscillators close to their drivers to minimize phase noise and startup issues.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/W90IOb5Uq46rHkqVwEGQ">/pages/W90IOb5Uq46rHkqVwEGQ</a></td><td>Ensure tight ground return loops for input and output paths to reduce EMI and voltage ripple.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/K93E9jzwkH8P11hi7pjq">/pages/K93E9jzwkH8P11hi7pjq</a></td><td>Ensure a stable, low-impedance signal path for power pins.</td><td>Automatically detected</td></tr></tbody></table>

### Validating constraints

Quilter uses Physics Rule Checks (PRCs) to determine if constraints defined in Circuit Comprehension are correctly implemented in each layout.&#x20;

You can find more information about the Physics Rule Checks provisioned for each constraint listed above in [Physics Rule Checks (PRCs)](/physics-rule-checks-prcs/overview).


# Review and edit constraints

An overview of Quilter’s Constraints step, outlining how to define and validate physics constraints for your PCB layout.

<figure><img src="/files/CZY0nil8q9JfDC0OS14R" alt=""><figcaption></figcaption></figure>

## Computed Constraints

### Differential Pairs

Based on the parameters from your stackup, Quilter uses Simbeor to calculate the correct trace width on each layer. Currently the frequency is assumed to be 1 GHz.

<figure><img src="/files/xR0WHQa76fNofYt0rbpe" alt=""><figcaption></figcaption></figure>

You can directly edit the width and gap here to override what we have calculated. This is especially useful if you have standard, precalculated values for your stackup.

### Power Nets

For each net and current you defined on the previous Comprehensions page, Quilter calculates the appropriate trace width to limit temperature rise to 20\*C, using the IPC-2221 definitions.

<figure><img src="/files/FRgvPib0aWTm8W8fLPXU" alt=""><figcaption></figcaption></figure>

## Define your own constraints

<figure><img src="/files/9NCNUOegzfuQZq7KqKq6" alt=""><figcaption></figcaption></figure>

### Net Widths by Layer

This allows you to specify trace width controls for nets. It is used rarely, and should probably be limited to nets that Quilter does not have another control for; e.g. you should not put in widths for your differential pairs here.

### Proximity Constraints

If Quilter does not have a placement control for your component type, you can add it here. One of the more common cases are protection diodes. You can also manually place components instead of using the placement constraints.


# Submit your layout job

Instructions on submitting a layout job to Quilter, including naming your job, processing times, and receiving candidate results.

Once you've uploaded valid input files, set physics constraints, and specified design parameters, you're ready to name and submit your layout job.

Quilter will generate a default name for the layout job from your design files, but you can override it here if you prefer.&#x20;

{% hint style="success" %}
**Renaming jobs**\
Don't worry – you can always rename your job later (see [Job Actions](/job-actions)).&#x20;
{% endhint %}

<figure><img src="/files/bXkhzCaqFLlTs6ciD6NZ" alt=""><figcaption></figcaption></figure>

Once you've submitted your job, you'll see a blank loading screen while Quilter explores the best layout options for your job.&#x20;

<figure><img src="/files/YOA6fiBCA8phG5VJMeDP" alt=""><figcaption></figcaption></figure>

Quilter's time to explore all layout candidates varies depending on the complexity of your job, ranging from 15 minutes to 24 hours. Typically, you'll get the first results back within an hour. Once returned, candidates are instantly available for review in the candidate sidebar.&#x20;

You'll receive an email when Quilter finds the first successful candidate for your layout job, and another email when the job is finished, along with a summary of the results.&#x20;


# Review layout candidates

Explanation of Quilter’s Candidate Review page, including evaluating successful and unsuccessful layout candidates, managing filters, and downloading results.

### Overview

Once Quilter has finished exploring layout options for a job, it marks it as "complete" and returns one of three different "results."

1. <mark style="background-color:green;">**Successful**</mark>**:** Quilter successfully identified >95% complete candidates.
2. <mark style="background-color:orange;">**Unsuccessful**</mark>**:** Quilter couldn't find any >95% complete candidates.
3. <mark style="background-color:red;">**Failed**</mark>**:** Quilter encountered an internal error or issue during the layout job and couldn't return *any* layout candidates.

On the Candidate Review page, you can:

* **Select candidates** by clicking them in the left-hand sidebar.
* **Inspect candidates** by clicking "Detail View" to toggle individual board layers and object types (see [Detail view](/candidate-review/detail-view)).
* **Review PRCs** for the selected candidate (see [Physics Rule Checks (PRCs)](/physics-rule-checks-prcs/overview)).
* **Download a placement** to modify the component locations, before reuploading it
* **Download a candidate** to inspect it offline in your preferred CAD tool and tweak the routing, or do a partial ripup before reuploading for Quilter to finish
* **Duplicate the job** to create a new draft layout job with the same files, physics constraints, and design parameters (see [Job Actions](/job-actions)).

{% hint style="danger" %}
**No candidates returned**
{% endhint %}

* If Quilter was entirely unable to return any layout candidates for your job, you will see the notification below.
* This usually means that Quilter encountered an error or issue while generating your layout job and failed to complete it.
* Clicking the "Send us a message" button will start a chat with the Quilter team so we can resolve the issue for you.

<figure><img src="/files/9nKFNNsuCfNlAGixMEvu" alt=""><figcaption></figcaption></figure>

###


# Overview

* overview of status
* link to view/vote on cad tool support


# Altium


# KiCAD


# Siemens Xpedition


# Cadence Allegro


# Other CAD tools


# Zuken CR-8000


# EasyEDA


# Overview

Explanation of how Quilter identifies, categorizes, and manages physics constraints during Circuit Comprehension, including automatic detection and manual specification.

During the Circuit Comprehension step, Quilter gathers key physics concerns from your design and converts them into various **physics constraints**.&#x20;

Quilter tries to automatically identify as many constraints as possible by analyzing the board and schematic files you provide. It uses a range of features from these files, including object and net classes, component and net names, pin names, connections, and the relative position of components.

There are two types of constraints:

### **Routing Constraints**

Routing Constraints impact the properties of traces and guarantee that key electrical characteristics stay within specified limits. Our current routing constraints are:

<table><thead><tr><th width="200.10791015625">Constraint</th><th width="399.79052734375">Details</th><th>Automatic?</th></tr></thead><tbody><tr><td><a data-mention href="/pages/6n6pBLMX9LH3mW3zGWDT">/pages/6n6pBLMX9LH3mW3zGWDT</a></td><td>Design high-current nets as traces with a specified width or as copper pours.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/FQkEcqQF14sKwWxhqUWU">/pages/FQkEcqQF14sKwWxhqUWU</a></td><td>Generate differential pairs with controlled lengths and impedances for high-speed digital signals.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/PYz2sZ6jr6LwiNiNHOhF">/pages/PYz2sZ6jr6LwiNiNHOhF</a></td><td>Impedance-controlled nets for RF nets or other fast, long, or sensitive traces.</td><td>Manual</td></tr><tr><td><a data-mention href="/pages/AWyphmkmhKFzQOw9o2MC">/pages/AWyphmkmhKFzQOw9o2MC</a> (coming soon)</td><td>Length matching for timing-sensitive interfaces such as DDR memory</td><td>Manual</td></tr></tbody></table>

### **Placement Constraints**

Placement Constraints help keep components tightly placed to reduce trace length. Our current placement constraints are:

<table><thead><tr><th width="199.79901123046875">Constraint</th><th width="400.1043701171875">Details</th><th>Automatic?</th></tr></thead><tbody><tr><td><a data-mention href="/pages/UoFdbNAFEuvp1pOFyMPf">/pages/UoFdbNAFEuvp1pOFyMPf</a></td><td>Position oscillators close to their drivers to minimize phase noise and startup issues.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/W90IOb5Uq46rHkqVwEGQ">/pages/W90IOb5Uq46rHkqVwEGQ</a></td><td>Ensure tight ground return loops for input and output paths to reduce EMI and voltage ripple.</td><td>Automatically detected</td></tr><tr><td><a data-mention href="/pages/K93E9jzwkH8P11hi7pjq">/pages/K93E9jzwkH8P11hi7pjq</a></td><td>Ensure a stable, low-impedance signal path for power pins.</td><td>Automatically detected</td></tr></tbody></table>

{% hint style="warning" %}
**All nets without constraints are routed as generic signals**\
Quilter treats all signals that aren't represented in Circuit Comprehension as generic, low-speed digital signals. If your physics constraints aren't yet supported by Quilter, we recommend pre-placing or pre-routing them before submission.
{% endhint %}

Every constraint has its own set of rules for detection and assignment. Knowing these rules can help you resolve edge cases or unexpected behavior. By using specific netclasses, patterns, and naming conventions, Quilter can identify your constraints. You'll find more details on this in the documentation that follows.&#x20;

Quilter also lets you manually enter any constraints you need to include.


# Power Nets

Explanation of Quilter’s Power Net constraint, including automatic detection criteria, recommended naming conventions, default current values, and IPC-based validation methods.

This constraint aims to establish the minimum trace widths needed to prevent excessive resistive heating on traces carrying high currents, and to allow the user to specify which nets should have power pours.

### Automatic Detection

Nets with certain attributes will be automatically classified as high current nets. This will include:

* Any net that matches our various patterns for being a voltage or power net.
* Any net in a "Power" netclass.

### Recommended Patterns

You can force Quilter to detect a power net by placing it in a "Power" net class. This is particularly helpful for nets that do not have a voltage-pattern name (like 3V3) but do need to carry a significant amount of current, such as a net that powers a motor.

### Defaults

We assign conservative default values to every automatically detected net, assuming they are unlikely to carry high current. If a net is expected to encounter a substantial amount of current, you should specify the maximum in the interface.

Nets with detected voltages under 3V are assigned a 200mA maximum current by default, and nets over 3V receive a maximum of 500mA.

### Constraint details

<figure><img src="/files/sGkkGoPT1Juit762P0YC" alt=""><figcaption></figcaption></figure>

Power nets can be set up in the "Power Nets" section of Circuit Comprehension. You can add them one by one, match them with regex, or use a netclass.&#x20;

To define a power net constraint, you'll need to fill in the following fields:

1. Net name
2. Maximum current (mA)
3. Optionally choose if you want that net to be a power pour

Quilter automatically completes IPC calculations that consider the specified copper weight and layer thickness for each stack-up to determine the ideal trace width for the net to prevent overheating.

### Physics Rule Checks

The PRCs that validate this constraint after compilation are:

**Overheated Length** determines the approximate analytic temperature rise of trace segments on a specified high current nets. A net segment is considered “overheated” if its approximated temperature rise exceeds 20C.


# Single-ended Impedance Control

Details on specifying and validating single-ended impedance-controlled nets, including supported impedances and calculation methods.

This constraint enables impedance-controlled routing for RF nets and other fast, long, or sensitive traces.&#x20;

### Automatic Detection

* Currently, single-ended impedance nets can only be entered manually.

### Constraint details

<figure><img src="/files/C6pFK40Zqn9MZpIH9ZyG" alt=""><figcaption></figcaption></figure>

Single-ended impedance control can be applied to nets in the "Single Ended Impedance Signals" section of Circuit Comprehension. You can add them one at a time, match them using regex, or apply a netclass. &#x20;

To define a high current net constraint, you need to fill in the following fields: &#x20;

1. Net name &#x20;
2. Target impedance (we currently support 50Ω and 75Ω) &#x20;
3. Signal frequency (GHz) &#x20;

Quilter will automatically perform the impedance control calculations that take into account the specified stack-up's material properties to determine the correct trace width necessary to achieve the specified impedance within a tolerance of 5%.

### Physics Rule Checks

The following PRCs validate this constraint after compilation:

**Invalid Width Span** determines the length of trace paths in a net are outside of an acceptable tolerance threshold. A trace segment has an “invalid width” if its width is outside of a 10% tolerance when compared to the nominal value.

**Ground Plane Overlap** determines if the ground plane below net traces overlaps at all relevant points.


# Differential Pairs

Instructions on defining differential pair constraints, including detection rules, limitations, supported impedances, and required fields.

Generates length and impedance-controlled differential pairs for high-speed digital signals.

{% hint style="warning" %}
**Differential Pair Routing Limitations**

Differential pair routing has the following limitations. We're working to expand these constraints to enable the development of more sophisticated designs:

1. Quilter **cannot currently route differential pairs with multiple receivers** ("multi-drop" or "fly-by" pairs). These will be detected but automatically ignored.
2. Quilter **avoids differential pairs on 2-layer stack-ups** to ensure they are always routed on top of a ground plane. We always route differential pairs as microstrip and are not yet able to do co-planar waveguide.
   {% endhint %}

### Automatic Detection

Nets with specific attributes will be automatically classified as differential pairs. The rules for this classification are:

* Nets must be in `differentialpair` or synonymous net class (`75ohm` etc)
* Net names must end in a set of supported paired suffixes that include any of the following:

<table><thead><tr><th width="120.1015625">Suffix</th><th width="178.6796875">Description</th><th>Example</th></tr></thead><tbody><tr><td><code>+</code> / <code>–</code> </td><td>Plus / Minus</td><td><code>TX+</code> and <code>TX-</code></td></tr><tr><td><code>A</code> / <code>B</code></td><td>A / B</td><td><code>SSTXA</code> and <code>SSTXB</code></td></tr><tr><td><code>P</code> / <code>M</code></td><td>Plus / Minus</td><td><code>RFoutP</code> and <code>RFoutM</code> (last character)<br>​<code>USB_DPX</code> and <code>USB_DMX</code> (second-to-last character)</td></tr><tr><td><code>P</code> / <code>N</code></td><td>Positive / Negative</td><td><code>DP</code> and <code>DN</code></td></tr><tr><td><code>t</code> / <code>c</code></td><td>True / Complement</td><td><code>ddr0_dqs_t</code> and <code>ddr0_dqs_c</code></td></tr></tbody></table>

{% hint style="info" %}
**Avoiding Power Nets**\
Quilter will not interpret net names that start with `V` as a differential pair to avoid confusion with power net names
{% endhint %}

### Recommended Patterns

Quilter starts by searching for accepted net classes, so make sure your pairs are part of an accepted net class. It then filters out net pairs ending with P and N to eliminate any single-ended impedance nets.&#x20;

**Pairs with inline resistors or capacitors**

Differential pairs with resistors or capacitors in series will be detected separately by their net names and displayed in the UI as two separate differential pairs. Don't worry, though - these are combined during compilation.

### Constraint Details

<figure><img src="/files/Gw3vzgKzcRuKg8bwisXy" alt=""><figcaption></figcaption></figure>

When Quilter detects a potential differential pair, it presents it for validation as part of the "Differential Pairs" section of the Circuit Comprehension step of job creation.

For each differential pair, you must specify:

* Positive paired net name
* Negative paired net name
* Target differential impedance
* Associated single-ended impedance
* Carrier frequency (in GHz)

Quilter uses this information to determine the appropriate trace width and spacing requirements for the specific stack-up that Quilter is using to generate your PCB layout.

If Quilter has incorrectly identified a differential pair, you can ignore it by clicking the `Remove` button on the row for that differential pair.

{% hint style="info" %}
**Supported differential impedance values**\
Differential/single-ended impedances are currently limited to 100Ω differential (50Ω single-ended) and 85Ω differential (42.5Ω single-ended). We plan to add support for fully customized differential and single-ended impedance requirements shortly.
{% endhint %}

### Physics Rule Checks

The PRCs that validate this constraint after compilation are:

**Length Mismatch** evaluates the difference in overall trace length between the two nets or the trace path between two pins in separate nets

**Uncoupled Spacing** calculates the maximum trace length in which the differential pair is uncoupled. The nominal spacing is determined based on desired differential impedance and the specific stackup. A differential pair trace segment is considered “uncoupled” if it’s projected distance from the other trace in the other net is outside of a tolerance of 10% when compared to the nominal spacing.

**Ground Plane Overlap** determines if the ground plane below net traces overlaps at all relevant points.

### FAQs

<details>

<summary>What is the highest frequency Quilter can handle?</summary>

Quilter's impedance control calculations are accurate and recommended for signals up to 6GHz.

</details>


# Timing-sensitive Signals

{% hint style="danger" %}
**In-development**\
Our Timing-sensitive signals constraint is currently in internal testing and not yet publicly available.
{% endhint %}

The timing-sensitive signals constraint enables precise control over signal delay and maximum delay skew within a set of signals for applications like HDMI and DDR.


# Bypass Capacitors

Guidelines for setting bypass capacitor constraints, including automatic detection criteria, recommended schematic practices, and required configuration details.

This constraint guarantees that bypass and decoupling capacitors are placed close to the correct pins.

### Automatic Detection

When bypass capacitors are connected between a component and ground, they're automatically detected.&#x20;

They're assigned to a parent pin using this priority order:

1. Explicit connection by wire in the schematic
2. Parent pins with voltage-type names (e.g. `Vin`)
3. If a capacitor is connected to multiple pins of the same name, it's split equally across them.

### Recommended Patterns

For a capacitor to be assigned correctly to a parent pin, the best approach is to connect it directly to the pin in the schematic with a wire. Other patterns, such as blocks of capacitors linked by a net label or power port, will still be interpreted using our rules, but with lower priority.&#x20;

You can also manually edit the assignment in the interface.

### Constraint Details

<figure><img src="/files/LDkSycXMGI3USkbUMHB3" alt=""><figcaption></figcaption></figure>

Configure bypass capacitor constraints in the "Bypass Capacitors" section of Circuit Comprehension.&#x20;

To set a bypass capacitor constraint, fill in the following fields:

* Capacitor (reference designator)
* Component being bypassed
* Pin on that component being bypassed
* Capacitance

Quilter automatically places capacitors with smaller capacitance values closer to power pins for a low-latency, low-impedance path. It can also position a single capacitor to bypass multiple pins on the same IC.

### Physics Rule Checks

The PRCs that validate this constraint after compilation are:

**Pin Distance** calculates the Euclidian distance between the closest edges of two pins.

**Layer Switch Count** finds the number of times there is a layer switch in a trace path between two pins

**Ground Plane Overlap** determines if the ground plane below net traces overlaps at all relevant points.

**Trace Path Length** calculates the trace length between two pins of interest.

### FAQs

<details>

<summary>Can Quilter handle multiple bypass capacitors for a single IC?</summary>

Yes, Quilter can identify and optimize one-to-many relationships between ICs and their bypass capacitors, ensuring effective decoupling across different frequency ranges.

</details>

<details>

<summary>How does Quilter decide where to place bypass capacitors?</summary>

Quilter strategically places smaller capacitors near high-current voltage sinks to minimize impedance and stabilize power delivery. The algorithm reduces trace lengths and via counts to lower parasitic effects in the decoupling network.

</details>

<details>

<summary>Can I override Quilter’s automatic placements?</summary>

Yes, you can manually adjust or pre-place bypass capacitors in your input file if you have specific design requirements.

</details>


# Crystal Oscillators

Instructions for defining crystal oscillator constraints, covering detection criteria, configuration fields, and current limitations.

This constraint is designed to position oscillators near their drivers, minimizing phase noise and startup problems.

### Automatic Detection

Crystal oscillators are automatically detected if they meet the following criteria:

* A crystal oscillator component with a reference designator begins with an `X` or `Y`&#x20;
* Both pins of the crystal oscillator are directly connected to the same parent component or driver.

{% hint style="warning" %}
**Load-limiting Resistors**\
This constraint currently does not detect or function on crystals with load-limiting resistors
{% endhint %}

### Constraint Details

<figure><img src="/files/4gMpainRI15Hrc71RCkt" alt=""><figcaption></figcaption></figure>

Set up crystal oscillator constraints in the "Crystal Oscillators" section of Circuit Comprehension.&#x20;

To add a crystal oscillator constraint, enter the following information:

* Crystal (reference designator)
* Parent component
* Parent pin 1
* Parent pin 2

If Quilter did not automatically detect your Crystal Oscillator, you can add it manually by pressing the `Add` button.&#x20;

### Physics Rule Checks

The PRCs that validate this constraint after compile are:

**Pin Distance** calculates the Euclidian distance between the closest edges of two pins.

**Layer Switch Count** finds the number of times there is a layer switch in a trace path between two pins

**Trace Path Length** calculates the trace length between two pins of interest.

**Ground Plane Overlap** determines if the ground plane below net traces overlaps at all relevant points.


# Switching Converters

Instructions for configuring switching converter constraints, covering detection criteria, supported configurations, and required fields.

This constraint ensures tight ground return loops for input and output paths, minimizing EMI and voltage ripple.&#x20;

This is a special case that applies only to switching converters with a specific configuration, consisting of two or more external capacitors (input and output capacitors) and an external output inductor. Other configurations are not supported and are generally unnecessary for achieving good results.&#x20;

During compilation, this constraint requires the three passive components to be positioned as closely as possible to the converter package.

### Automatic Detection

Certain switching converters will be detected automatically:

* The reference designator for the switching converter must begin with `U`
* The switching converter output connects to an inductor with a reference designator that begins with `L`&#x20;

Quilter can handle regulator configurations with multiple input or output capacitors, but will somewhat arbitrarily select one for the purposes of constraining switching coverter placement.

{% hint style="info" %}
**Regulator Not Detected**\
If your converter/regulator is not detected, this is not a cause for concern, and the compilation process will work fine
{% endhint %}

### Constraint Details

<figure><img src="/files/rM37Ke0tLsrgszbwsUCy" alt=""><figcaption></figcaption></figure>

Set up switching regulator constraints in the "Switching Converters" section of Circuit Comprehension.&#x20;

To add a switching converter constraint, enter the following information:

* Switching converter (reference designator, must begin with `U`)
* Output inductor (reference designator, must begin with `L`)
* (optional) Input capacitor&#x20;
* (optional) Output capacitor

If Quilter did not automatically detect your Switching Converter, you can add it manually by pressing the `Add` button.&#x20;

### Physics Rule Checks

The PRCs that validate this constraint after compile are:

**Pin Distance** calculates the Euclidian distance between the closest edges of two pins.

**Layer Switch Count** finds the number of times there is a layer switch in a trace path between two pins

**Trace Path Length** calculates the trace length between two pins of interest.

**Ground Plane Overlap** determines if the ground plane below net traces overlaps at all relevant points.


# Overview

Overview of Physics Rule Checks (PRCs) applied by Quilter to validate user-defined physics constraints.

Physics rule checks (PRCs) validate candidates by ensuring that the critical parameters for each physics constraint are satisfied. Quilter produces PRC reports for every layout candidate it examines.

During Circuit Comprehension, Quilter reads your schematic and input board file to automatically detect  [Physics Constraints](/physics-constraints/overview) that capture the core physics concerns in your design. Quilter generates a set of PRCs for each identified constraint as a way to evaluate the implementation of that constraint in the layout candidates that it generates.

For example, [Differential Pairs](/physics-constraints/differential-pairs)are checked to validate appropriate length matching, tightly coupled spacing, and ground plane overlap.

Continue reading for a complete overview of supported Physics Rule Checks and the associated physics constraints that they support.

### PRCs by Constraint Type

<table><thead><tr><th width="312.484375">Physics Constraint</th><th>Applied PRCs</th></tr></thead><tbody><tr><td><a data-mention href="/pages/6n6pBLMX9LH3mW3zGWDT">/pages/6n6pBLMX9LH3mW3zGWDT</a></td><td><ul><li><a data-mention href="/pages/5ZE2ebhYkOpr7vT8hKZy">/pages/5ZE2ebhYkOpr7vT8hKZy</a></li></ul></td></tr><tr><td><a data-mention href="/pages/AWyphmkmhKFzQOw9o2MC">/pages/AWyphmkmhKFzQOw9o2MC</a></td><td>Coming soon</td></tr><tr><td><a data-mention href="/pages/PYz2sZ6jr6LwiNiNHOhF">/pages/PYz2sZ6jr6LwiNiNHOhF</a></td><td><ul><li><a data-mention href="/pages/7gK0UEHzuo2c70iU2Wqi">/pages/7gK0UEHzuo2c70iU2Wqi</a></li><li><a data-mention href="/pages/kZyvCPEEwFj5ncNj5uQP">/pages/kZyvCPEEwFj5ncNj5uQP</a></li></ul></td></tr><tr><td><a data-mention href="/pages/FQkEcqQF14sKwWxhqUWU">/pages/FQkEcqQF14sKwWxhqUWU</a></td><td><ul><li><a data-mention href="/pages/kZyvCPEEwFj5ncNj5uQP">/pages/kZyvCPEEwFj5ncNj5uQP</a></li><li><a data-mention href="/pages/i7MqPlfn0pLBmzgldYhA">/pages/i7MqPlfn0pLBmzgldYhA</a></li><li><a data-mention href="/pages/FDDAwhRQA8dMk4tnNYkA">/pages/FDDAwhRQA8dMk4tnNYkA</a></li></ul></td></tr><tr><td><a data-mention href="/pages/K93E9jzwkH8P11hi7pjq">/pages/K93E9jzwkH8P11hi7pjq</a></td><td><ul><li><a data-mention href="/pages/POosPNVfqA7hgqDWTW0J">/pages/POosPNVfqA7hgqDWTW0J</a></li><li><a data-mention href="/pages/kaZ8bSj1PYqvjPebcBwD">/pages/kaZ8bSj1PYqvjPebcBwD</a></li><li><a data-mention href="/pages/JH9rYcLM7XpZf8WbGrPN">/pages/JH9rYcLM7XpZf8WbGrPN</a></li><li><a data-mention href="/pages/kZyvCPEEwFj5ncNj5uQP">/pages/kZyvCPEEwFj5ncNj5uQP</a></li></ul></td></tr><tr><td><a data-mention href="/pages/UoFdbNAFEuvp1pOFyMPf">/pages/UoFdbNAFEuvp1pOFyMPf</a></td><td><ul><li><a data-mention href="/pages/POosPNVfqA7hgqDWTW0J">/pages/POosPNVfqA7hgqDWTW0J</a></li><li><a data-mention href="/pages/kaZ8bSj1PYqvjPebcBwD">/pages/kaZ8bSj1PYqvjPebcBwD</a></li><li><a data-mention href="/pages/JH9rYcLM7XpZf8WbGrPN">/pages/JH9rYcLM7XpZf8WbGrPN</a></li><li><a data-mention href="/pages/kZyvCPEEwFj5ncNj5uQP">/pages/kZyvCPEEwFj5ncNj5uQP</a></li></ul></td></tr><tr><td><a data-mention href="/pages/W90IOb5Uq46rHkqVwEGQ">/pages/W90IOb5Uq46rHkqVwEGQ</a></td><td><ul><li><a data-mention href="/pages/POosPNVfqA7hgqDWTW0J">/pages/POosPNVfqA7hgqDWTW0J</a></li><li><a data-mention href="/pages/kaZ8bSj1PYqvjPebcBwD">/pages/kaZ8bSj1PYqvjPebcBwD</a></li><li><a data-mention href="/pages/JH9rYcLM7XpZf8WbGrPN">/pages/JH9rYcLM7XpZf8WbGrPN</a></li><li><a data-mention href="/pages/kZyvCPEEwFj5ncNj5uQP">/pages/kZyvCPEEwFj5ncNj5uQP</a></li></ul></td></tr></tbody></table>

### PRC Results

<figure><img src="/files/hgcH7gtjfEDO7crdtJz1" alt=""><figcaption><p>Example PRC result for a Bypass Capacitor constraint</p></figcaption></figure>

During the review step, you will see passing and failing PRCs alongside candidates, allowing you to be confident that the design will work as expected. For failing PRCs, the documentation for each PRC provides more insight into the listed error.

For more information on interpreting PRC results, see [Reviewing PRCs](/reviewing-prcs).


# Ground Plane Overlap

Explanation of the Ground Plane Overlap PRC, verifying consistent ground coverage beneath impedance controlled signals to ensure signal integrity and minimize EMI.

### Description

**Ground Plane Overlap** determines if the ground plane below a specified net traces overlaps at all relevant points.&#x20;

Relevant points are defined outside a small margin provided in order to account for cutouts around the attached pins and vias.

**Passing Criteria:** \
This check passes if there is complete overlap of both sides of the differential pair with the ground plane on the layer below it at all locations except the last 2\*clearance length endpoints of the trace paths.

**Reporting Units:** \
BOOLEAN

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Complete Ground Plane Overlap is True
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Complete Ground Plane Overlap is False
{% endhint %}

### Physics Justification

Sufficient ground plane coverage below all traces in a net addresses the following: &#x20;

* **Signal Return Path**  \
  The ground plane provides a low-impedance return path for current, which reduces electromagnetic interference (EMI) and enhances signal integrity. &#x20;
* **Controlled Impedance** \
  The space between the trace and the ground plane determines the trace's **impedance**. This must remain consistent for high-speed signals to prevent reflections and distortion. &#x20;
* **Noise Shielding**  \
  The ground plane acts as a shield, minimizing external noise and preventing crosstalk—the interference between signals.


# Invalid Width Span

Summary of the Invalid Width Span PRC, ensuring trace widths remain within acceptable tolerances for impedance control, current capacity, and EMI mitigation.

### Description

**Invalid Width Span** determines the length of trace paths in a net are outside of an acceptable tolerance threshold. A trace segment has an “invalid width” if its width is outside of a 10% tolerance when compared to the nominal value.

For the *Net Width* comprehension, the expected width is explicitly defined, while for the *Single-ended Impedance Signal* comprehension, the nominal width is determined based on impedance and stackup characteristics.&#x20;

**Passing Criteria:** \
This check passes if the length of trace segments that are **outside** the width tolerance falls below an acceptable percentage. If the acceptable percentage is not met (in the case of short nets), a fallback acceptable length tolerance is used. If neither of these criteria is met, the failed percentage is reported

**Reporting Units:** \
Length PERCENTAGE (%) or CENTIMETERS (cm)

### **Examples**

**Passing Messages:**&#x20;

{% hint style="success" %}
Invalid width span of 1.05% within acceptable range (0% to 10%)
{% endhint %}

{% hint style="success" %}
Invalid width span of 0.17cm within acceptable range (0cm to 1cm)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Invalid width span of 87.06% outside acceptable range (0% to 10%)
{% endhint %}

### Physics Justification

* **Controlled Impedance**

  The trace width, along with the dielectric material and distance to the reference plane, determines impedance. An incorrect width can cause reflections, signal distortion, and poor signal integrity.
* **Current Carrying Capacity**

  The trace width affects how much current the trace can safely handle without excessive heat. A too-narrow trace can lead to overheating and potential damage.
* **Electromagnetic Interference (EMI)**

  Proper trace width reduces EMI by maintaining consistent transmission line behavior, which cuts down on noise and radiation.
* **Design Consistency**

  The layer stackup defines the PCB's physical and electrical properties, so deviating from specified widths can throw off expected performance.

#### Helpful Definitions

* **Electromagnetic Interference (EMI)**\
  Unwanted electromagnetic radiation or coupling that disrupts the operation of nearby electronic devices or circuits.


# Layer Switch Count

Summary of the Layer Switch Count PRC, verifying minimal via count between bypass capacitors and associated pins to maintain low impedance and effective decoupling.

### Description

**Layer Switch Count** finds the number of times there is a layer switch in a trace path between two pins

**Passing Criteria:** \
This check passes if the number of vias on the path between a bypass capacitor and its associated pin is below a specified threshold.

**Reporting Units:** \
COUNT

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Layer switch count of 0 within acceptable range (0 to 1)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Layer switch count of 2 outside acceptable range (0 to 1)
{% endhint %}

### Physics Justification

Layer switches on trace paths between pins introduce **parasitic inductance**, which:&#x20;

* **Reduces Filtering Effectiveness**&#x20;

  Parasitic inductance degrades the ability to respond to high-frequency noise.&#x20;
* **Increases Impedance**&#x20;

  Vias add impedance to the path, disrupting the low-impedance connection needed for proper **decoupling** in the case of bypass capacitors.&#x20;
* **Affects Power Stability**&#x20;

  Higher impedance and slower response times can cause voltage fluctuations at the pin, impacting the power integrity of the connected component.

#### Helpful Definitions

* **Parasitic Inductance**\
  The unintended inductance that arises from the magnetic field created by current flow and opposes changes in current, especially at high frequencies. It can degrade circuit performance by slowing responses and causing noise.
* **Decoupling**\
  The use of capacitors placed near pins to stabilize voltage and filter out noise on the power supply.


# Length Mismatch

### Description

**Length Mismatch** evaluates the difference in overall trace length between the two nets or the trace path between two pins in separate nets

**Passing Criteria:** \
This check passes when the absolute length difference between the two sides of the differential pair falls below a specified tolerance.

**Reporting Units:** \
Length in CENTIMETERS (cm)

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Length mismatch of 0.27cm within acceptable range (0cm to 1cm)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Length mismatch of 2.57cm outside acceptable range (0cm to 1cm)
{% endhint %}

### Physics Justification

Length matching in differential pair traces is crucial for ensuring that the signals arrive at the receiver simultaneously, thus maintaining their **phase alignment**. In particular:

* **Noise Cancellation**

  Differential pairs rely on signals being exact opposites. If they’re misaligned, they cannot cancel external noise effectively, which reduces signal integrity.
* **Avoiding Mode Conversion**

  Length mismatches can convert the differential signal into **common-mode noise**, leading to interference and degraded performance.
* **Signal Timing**

  In high-speed circuits, even small timing differences caused by mismatched lengths can introduce errors in data transmission.

#### Helpful Definitions

* **Phase Alignment**

  This refers to two signals in a pair (like a differential pair) staying in sync and reaching their destination at the same time. Misalignment can distort the signal and cause errors.
* **Mode Conversion**

  This occurs when differential signals (opposites) lose their balance because of mismatched traces, causing part of the signal to change into **common-mode noise**, which is unwanted.
* **Common-Mode Noise**

  This is noise shared by both signals in a pair, caused by imbalances or interference, disrupting the signal the circuit is trying to read.&#x20;


# Overheated Length

### Description

**Overheated Length** determines the approximate analytic temperature rise of trace segments on a specified high current nets. A net segment is considered “overheated” if its approximated temperature rise exceeds 20C.

**Passing Criteria:** \
This check passes if less than a specified percentage of the length of traces within the high current net has a temperature rise below a given threshold.

**Reporting Units:** \
Length Percentage (Tolerance: Celsius)

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Overheated length of 0% within acceptable range (0% to 10%)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Overheated length of 56.2% outside acceptable range (0% to 10%)
{% endhint %}

### Physics Justification

Minimizing the temperature rise of high-current nets is important for the following reasons:

* **Resistive Heating (Joule Heating)** &#x20;

  High current flowing through a trace causes **I²R losses**, where electrical resistance (**R**) converts current (**I**) into heat. Excessive heat can damage the PCB or nearby components.
* **Board Performance** &#x20;

  An increased temperature (**T)** raises the resistance of the trace (**R**∝**T**), leading to more heat in a feedback loop, which can degrade signal integrity and power delivery.
* **Thermal Expansion** &#x20;

  Heat causes the PCB material to expand, potentially resulting in mechanical stress, delamination, or cracks in the copper traces.
* **Electromigration** &#x20;

  High temperatures accelerate **electromigration**, where metal atoms move due to current flow, degrading the trace over time and potentially causing failure.

#### Helpful Definitions &#x20;

* **Electromigration**  \
  The gradual movement of metal atoms within a conductor caused by the flow of high electrical current. This occurs because the momentum transfer from moving electrons pushes atoms along the current's path. Over time, it can create voids or buildup in the conductor, leading to increased resistance or signal degradation.


# Pin Distance

Summary of the Pin Distance PRC, checking pin spacing to ensure short traces, reduced EMI, and improved routing efficiency.

### Description

**Pin Distance** calculates the Euclidian distance between the closest edges of two pins.

**Passing Criteria:** This check passes is the pin distance falls below a specified tolerance

**Reporting Units:** \
CENTIMETERS (cm)

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Pin distance of 0.13cm within acceptable range (0cm to 1cm)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Pin distance of 1.11cm outside acceptable range (0cm to 1cm)
{% endhint %}

### Physics Justification

Minimizing the pin distance is important because it:&#x20;

* **Reduces Trace Lengths** \
  Shorter traces mean lower parasitic inductance and resistance, which improves signal integrity and power delivery.
* **Minimizes Loop Area** \
  Smaller loops reduce susceptibility to electromagnetic interference (EMI) and radiated noise.
* **Improves Routing Efficiency** \
  Compact pin placement contributes to cleaner and more manageable routing, especially in densely designed circuits.


# Trace Path Length

Summary of the Trace Path Length PRC, validating trace lengths to minimize inductance, enhance noise filtering, and ensure efficient power and signal integrity.

### Description

**Trace Path Length** calculates the trace length between two pins of interest.

**Passing Criteria:** \
This check passes if the calculated trace length falls below a specified tolerance

**Reporting Units:** \
CENTIMETERS (cm)

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Trace path length of 0.73cm within acceptable range (0cm to 1cm)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Trace path length of 2.95cm outside acceptable range (0cm to 1cm)
{% endhint %}

### Physics Justification

Minimizing the trace length is important because:&#x20;

* **Reduced Parasitic Inductance**:&#x20;

  Longer traces introduce **parasitic inductance**, degrading the ability to respond to high-frequency noise.&#x20;
* **Improved Noise Filtering**:&#x20;

  A short trace allows a capacitor to quickly supply or absorb current, effectively stabilizing the voltage and filtering noise.&#x20;
* **Lower Impedance Path**:&#x20;

  Shorter traces decrease impedance, ensuring robust and efficient power/signal delivery to the pin.&#x20;

#### Helpful Definitions&#x20;

* **Parasitic Inductance** \
  The unintended inductance present, which arises from the magnetic field created by current flow and opposes changes in current, especially at high frequencies. It can degrade circuit performance by slowing responses and causing noise.


# Uncoupled Spacing

Summary of the Uncoupled Spacing PRC, checking differential pair spacing to ensure effective electromagnetic coupling, consistent impedance, and minimal crosstalk.

### Description

**Uncoupled Spacing** calculates the maximum trace length in which the differential pair is uncoupled. The nominal spacing is determined based on desired differential impedance and the specific stackup. A differential pair trace segment is considered “uncoupled” if it’s projected distance from the other trace in the other net is outside of a tolerance of 10% when compared to the nominal spacing.

**Passing Criteria:** \
This check passes if the trace length of uncoupled spacing between the two trace paths in the nets of interest is below a specified length tolerance

**Reporting Units:** \
CENTIMETERS (cm)

### **Examples**

**Passing Message:**&#x20;

{% hint style="success" %}
Uncoupled spacing of 0.06cm within acceptable range (0cm to 1cm)
{% endhint %}

**Failing Message:**&#x20;

{% hint style="danger" %}
Uncoupled spacing of 6.57cm outside acceptable range (0cm to 1cm)
{% endhint %}

### Physics Justification

The distance between differential pairs is important because it affects how well they work together and resist interference. A few reasons why this is important include:

* **Electromagnetic Coupling**

  Differential pairs create small electromagnetic fields as signals travel. If the traces are too far apart, they won’t couple well, reducing their ability to cancel out external noise. Conversely, if they’re too close, they might interfere with each other or with other signals.
* **Crosstalk**

  If differential pairs are too close to other traces, their signals can interfere with neighboring traces (or vice versa), causing **crosstalk**, which is unwanted noise from other signals.
* **Impedance Control**

  The spacing affects the **differential impedance**, which is the resistance the signals encounter. Maintaining a specific distance ensures the impedance remains consistent, helping the signal to stay clear and fast.

#### Helpful Definitions

* **Crosstalk**

  Crosstalk is unwanted interference caused by signals in one trace inducing noise into a nearby trace. It happens because the electromagnetic fields from one trace can "leak" into another, disrupting the signal.
* **Differential Impedance**

  Differential impedance is the combined resistance a differential pair encounters as signals travel together. It's determined by the trace width, spacing between the traces, and the surrounding materials. Proper impedance ensures the signal integrity without reflections or losses.


# Future PRC2s


# Top Plane Ground Pour


# Neck Downs


# Trace Proximity


# Overview

Overview of Design Parameters available to constrain and specify Quilter-generated layouts.

**Design Parameters** are key design considerations that determine the options available to Quilter when generating layout candidates. These parameters cover everything from high-level questions, such as *who will manufacture your board,* to low-level details, like *where to place a capacitor.*

Once your board's Design Parameters are fully defined, your layout candidate is complete. Your input file is the main way to tell Quilter which Design Parameters (design elements) are fixed and which remain flexible for Quilter to explore.

We typically categorize Design Parameters into three main groups:

1. **Fabrication parameters** – who will manufacture your board, and what fabrication capabilities and materials do they have?
2. **Placement parameters** – where do components go on your design?
3. **Routing parameters** – how should components be connected?

As mentioned in [our introduction](/using-quilter/select-your-stackup), Design Parameters can be either requirements that Quilter *must* follow or *preferences* that act as filters on the solution space Quilter explores.

Check out the tables below to learn how to control Quilter's options and key parameters of the candidates it generates.

### Fabrication

In a traditional design workflow, fabrication parameters are fixed before the design process starts. Quilter reverses this approach, allowing you to consider the fabricator, fabrication rules, and even the stack-up as variables within the solution space that Quilter can explore and optimize.

By switching fabrication parameters from constraints to optimization variables, you can do amazing things with Quilter, including:

1. **Compile for multiple fabricators.** Create a single design that can be compiled for multiple fabricators and stack-ups, then send it to the manufacturer with the lowest cost or fastest turnaround time.
2. **Analyze performance vs. speed and cost.** Compile the same design with different fabrication rules (3.5 mil, 5 mil, and 6 mil) to explore the trade-offs between physics performance, layer count, and fabrication cost/speed.
3. **Optimize board density.** Compile the same design with various board outlines to examine the relationship between board size, component density, and layer count/routability.

<table><thead><tr><th width="161.1875">Parameter</th><th width="328.14453125">Description</th><th>Preference</th><th width="134.65625">Requirement</th></tr></thead><tbody><tr><td><a data-mention href="/pages/UAbcuyp5se6YcH5hjtm4">/pages/UAbcuyp5se6YcH5hjtm4</a></td><td>The PCB manufacturer that a specific layout candidate (stackup and fabrication ruleset) is designed for. </td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Filter by fabricator</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Enteprise customers only</td></tr><tr><td><a data-mention href="/pages/ZbYbLZzQ3agYsIweMCEU">/pages/ZbYbLZzQ3agYsIweMCEU</a></td><td>The stackup that Quilter uses when generating your candidate, including layer count, copper weight, material properties, and more.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Layer count only</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Stackup from input files</td></tr><tr><td><a data-mention href="/pages/DjgbihBmHtIOyB3xskYJ">/pages/DjgbihBmHtIOyB3xskYJ</a></td><td>Basic design rules that ensure your board can be manufactured without issue – trace, space, drill, via, edge clearances, etc</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Trace and space</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Design rules from input files</td></tr></tbody></table>

### Placement

Placement parameters let you control where Quilter places components on your board, ensuring the layout candidates it generates meet your design requirements and preferences. Specifically, you can use placement parameters to:

1. **Prefer placement to one side** for easy assembly and testing
2. **Enforce a specific "floor plan"** that meets 3D mechanical requirements and signal flow

<table><thead><tr><th width="161.1875">Parameter</th><th width="328.14453125">Description</th><th>Preference</th><th>Requirement</th></tr></thead><tbody><tr><td><a data-mention href="/pages/EcoVcR3CKIcqpYqjB5h7">/pages/EcoVcR3CKIcqpYqjB5h7</a></td><td>Lock the location of location-sensitive components so Quilter can't modify it.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2b07">⬇️</span> Use "placement regions"</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Place within board outline in input file</td></tr><tr><td><a data-mention href="/pages/Vvl4M5yhRVPlMSzhQ6hW">/pages/Vvl4M5yhRVPlMSzhQ6hW</a></td><td>Restrict Quilter's placement of unplaced components to a designated area within your board outline.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="274c">❌</span> Placement regions are always respected</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Add to input board file</td></tr><tr><td><a data-mention href="/pages/hXVfJU2UbeXSaGsgMikL">/pages/hXVfJU2UbeXSaGsgMikL</a></td><td>Limit placement to one side of the PCB.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Filter for single-sided designs.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2b06">⬆️</span> Use "placement regions"</td></tr></tbody></table>

### Routing

Routing Parameters help you influence and control how Quilter implements your board's netlist, to ensure that the layout candidates Quilter generates meet all of your electrical requirements and preferences.

Routing parameters can be used to:

1. **Define a custom stackup** that includes power planes dedicated to specific nets within your design&#x20;
2. **Assert custom net widths** for specific nets or net classes to override or supplement the [Fabricator constraints](/using-quilter/fabricator-constraints)for a particular layout job

<table><thead><tr><th width="161.1875">Parameter</th><th width="328.14453125">Description</th><th>Preference</th><th>Requirement</th></tr></thead><tbody><tr><td><a data-mention href="/pages/Gi93ywL7IY5D7fsi13ho">/pages/Gi93ywL7IY5D7fsi13ho</a></td><td>Lock the routing path of sensitive signals.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="274c">❌</span> Pre-routed traces are always preserved</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Leave within board outline in input file</td></tr><tr><td><a data-mention href="/pages/8uMnhPLSzjJHr92fRwhs">/pages/8uMnhPLSzjJHr92fRwhs</a></td><td>Preserve existing copper pours from your input pile for Quilter to use when generating candidates.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="274c">❌</span> Preserved pours are always respected</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> "Lock" pours you want to preserve in input ful</td></tr><tr><td><a data-mention href="/pages/YwcOS2w5Bv358iaMGmbm">/pages/YwcOS2w5Bv358iaMGmbm</a></td><td>Prevent Quilter from routing traces through specific geometric areas within your design.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="274c">❌</span> Keepouts are always respected</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Add keepout to your input file</td></tr><tr><td><a data-mention href="/pages/avcHOKpvovo3AuY05Q6W">/pages/avcHOKpvovo3AuY05Q6W</a></td><td>Manually specify net widths for individual nets or net classes in your design.</td><td><span data-gb-custom-inline data-tag="emoji" data-code="274c">❌</span> Net widths are always respected</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span> Specify "Net Width" in during job setup</td></tr></tbody></table>


# Fabricators

Explanation of Quilter’s fabricator profiles, including stack-ups, fabrication rules, compile targets, filtering options, and pre-supported manufacturers.

Quilter gives you the ability to generate layouts that utilize stack-ups and fabrication rules sourced directly from fabricators, as well as a beta feature for reading them from your input files.&#x20;

### Fabricator profiles

A **fabricator profile** contains information about the stack-ups and fabrication rules that a PCB manufacturer supports and that Quilter will use when exploring layouts intended for that fabricator.&#x20;

Fabricator profiles consist of:&#x20;

* [Stackups](/design-parameters/stackups), which define the physical parameters of your board, such as layer count, copper weight, and key material properties impacting physics calculations.
* [Fabricator constraints](/using-quilter/fabricator-constraints), which determine the geometric limitations of the particular fabrication service that the fabricator will use to manufacture your layout. Examples include minimum copper trace width and clearances.&#x20;

Each candidate that Quilter explores references a stack-up and fabrication rule set supported by the fabricator, as defined by the fabrication profile. We refer to this intersection of stack-up and fabrication rulesets as a "compile target."&#x20;

### Custom fabricator profiles

Quilter offers fabrication profile customization and implementation as a service to all paid customers. Customers can work with Quilter to define one or more custom fabrication profiles that utilize the stack-ups and fabrication rules that match the capabilities of their typical fabrication partners.

### Detected fabricator profile from user input files

ECAD tools generally save a stack-up and fabrication rules (DRC rules, in many cases) to your files. If you have intentionally configured them and not left the settings on defaults, you may want to try this feature.&#x20;

<figure><img src="/files/0iHPlFuG6bGBVqaleqt1" alt=""><figcaption></figcaption></figure>

### Pre-defined fabricators

For convenience, Quilter has pre-defined fabrication profiles for each of the following fabricators:

<table><thead><tr><th width="167.265625">Fabricator</th><th width="298.21875">Description</th><th>Location</th><th>Website</th></tr></thead><tbody><tr><td>JLCPCB</td><td>High-volume, low-cost PCB manufacturer with rapid turnaround.</td><td>China</td><td><a href="https://jlcpcb.com">jlcpcb.com</a></td></tr><tr><td>MacroFab</td><td>North American contract manufacturer offering prototyping to production.</td><td>Houston, TX, USA</td><td><a href="https://macrofab.com">macrofab.com</a></td></tr><tr><td>OSH Park</td><td>Community-focused PCB prototyping service for small-batch orders.</td><td>Oregon, USA</td><td><a href="https://oshpark.com">oshpark.com</a></td></tr><tr><td>CircuitHub</td><td>Turnkey PCB assembly service integrated with online BOM sourcing.</td><td>Massachusetts, USA</td><td><a href="https://circuithub.com">circuithub.com</a></td></tr><tr><td>American Standard Circuits</td><td>Full-service PCB manufacturer specializing in advanced and RF designs.</td><td>West Chicago, IL, USA</td><td><a href="https://www.asc-i.com">asc-i.com</a></td></tr></tbody></table>

### Example: OSH Park&#x20;

Here's an example "Fabrication Profile" for OSH Park, one of our [#pre-supported-fabricators](#pre-supported-fabricators "mention"), that specifies 12 unique Oshpark compile targets that align against OSH Park's [fabrication service capabilities](https://docs.oshpark.com/services/) and can be explored in parallel each time Quilter generates layout candidates.

<table><thead><tr><th width="171.421875">Fabrication Rules</th><th width="182.921875"></th><th>Stackup: 2 Layer Standard</th><th>Stackup: 4-Layer Standard</th><th>Stackup: 6-Layer Standard</th></tr></thead><tbody><tr><td><strong>Common_10_mil</strong></td><td>• 10 mil trace/space<br>• 12 mil drill</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td></tr><tr><td><strong>Common_8_mil</strong></td><td>• 8 mil trace/space<br>• 12 mil drill</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td></tr><tr><td><strong>Oshpark_2_Layer</strong></td><td>• 6 mil trace/space<br>• 10 mil drill</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td></tr><tr><td><strong>Oshpark_4_Layer</strong><br></td><td>• 5 mil trace/space<br>• 10 mil drill</td><td><span data-gb-custom-inline data-tag="emoji" data-code="1f534">🔴</span> Not supported by fabricator</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td></tr><tr><td><strong>Oshpark_6_Layer</strong><br></td><td>• 5 mil trace/space<br>• 8 mil drill</td><td><span data-gb-custom-inline data-tag="emoji" data-code="1f534">🔴</span> Not supported by fabricator</td><td><span data-gb-custom-inline data-tag="emoji" data-code="1f534">🔴</span> Not supported by fabricator</td><td><span data-gb-custom-inline data-tag="emoji" data-code="2705">✅</span></td></tr></tbody></table>

### How to specify

You can easily select the target fabricator that Quilter uses to generate candidates. On the Stackups page, select the fabricators and parameters you wish to see at the candidate review, and Quilter will attempt to place and route using those requirements.


# Stackups

Quilter generates PCB candidates using either the stackup from your files or standard stackups defined in partnership with top fabricators

### Overview

Stackups describe how layers and materials are arranged on a printed circuit board (PCB). A complete stackup includes the following information:

* Board thickness
* Number of layers\
  Purpose of each layer (signal, ground, power)
* Type of material used in each layer, including key details like dissipation factor (Df) and dielectric constant (Dk)
* Thickness of each layer and copper layer
* and more!

All ECAD tools supported by Quilter let you specify these details as part of your board's stackup.&#x20;

### How Quilter uses stackups

Physics constraints that depend on stackup details – like differential pairs and high current nets – are always tailored to the stackup details Quilter is compiling for.&#x20;

Quilter can read and write stackup information to the native CAD files you upload and download from our platform. Quilter always writes information about the stack-up it used to the downloaded board file to support a thorough design review.

### Stackup from your input files

The stackup and design minimums from your files will be an option at the top of the Stackups step, if they have been configured and detected correctly.&#x20;

<figure><img src="/files/9y0oNNkhJj3vj1uGAEY4" alt=""><figcaption></figcaption></figure>

{% hint style="warning" %}
**Make sure to name ground layers "ground" or "gnd" and power layers "power" or "pwr" so that Quilter will respect that intent when compiling your board.**
{% endhint %}

### Pre-defined Quilter stackups <a href="#h_4d3a642408" id="h_4d3a642408"></a>

For each layout candidate Quilter generates, it uses a specific stackup and associated material properties. These are used to test routing strategies and complete the necessary physics calculations for implementing signals that are sensitive to physics, such as [differential pairs](/physics-constraints/differential-pairs).

We've predefined standard stackups with our preferred fabrication partners, including JLCPCB, MacroFab, and CircuitHub.

<figure><img src="/files/PqK0V56EHuDzPYFQFZfC" alt=""><figcaption></figcaption></figure>


# Pre-placed components

Explanation of Quilter’s handling of pre-placed components, including reasons for pre-placement, supported scenarios, and instructions for locking positions.

### Overview

Quilter treats all components within the board boundary at upload as "pre-placed."&#x20;

**As a core principle, Quilter doesn't change the position or orientation of pre-placed components.**&#x20;

When compiling, Quilter will place and route components that were left outside the board outline.

{% hint style="success" %}
**Overhanging Components**\
Quilter can handle pre-placed components with overhanging design elements or component outlines, such as an ESP32 module with a PCB trace antenna positioned off the edge of the circuit board.
{% endhint %}

Learn more in the Placement Guide:

{% content-ref url="/pages/Y8GGLZBmEKqzIBx5VifQ" %}
[Placement Guide](/guides/placement-guide)
{% endcontent-ref %}

### Why should I pre-place components?

There are a few reasons to pre-place components:

1. **Location-sensitive components**\
   One main reason to pre-place a component is to make sure that location-sensitive parts, such as mechanical pieces and connectors, end up in the right spot. <br>
2. **Unsupported physics constraints**\
   If Quilter doesn't currently support a physics constraint that demands precise or highly organized placement of components, you can manually position individual components or groups to ensure they're placed correctly. <br>
3. **"Saving your progress"**\
   When working with Quilter, you might find that you like certain elements of a layout candidate, but not the overall design. Once you've downloaded a candidate, you can choose to keep the routing and placements you like, remove the rest, and resubmit to Quilter to save your progress towards a fabrication-ready design.

### How to specify

#### As a preference

Components inside the board outline are locked and can't be moved or rotated by Quilter during compilation. We won't change pre-placed components, even if they stop Quilter from finishing a layout job successfully.&#x20;

If you wish to constrain component placement to pre-specified sides or areas within your board outline, see [Placement regions](/design-parameters/placement-regions).

#### As a requirement

Locking the position and rotation of a component is easy: just pre-place it within the board outline and upload your input file to Quilter.


# Placement regions

Explanation of Quilter’s Placement Regions, including creation methods in Altium and Cadence, component associations, and instructions for constraining component placement.

### Overview

Placement Regions allow you to limit component placement by ensuring that components tied to the region are positioned within its geometric boundaries during compilation.

To set up a Placement Region, define a polygon object in your native ECAD input file, place it so it overlaps the board outline, and link it to either the top or bottom layer.&#x20;

Once you've uploaded your input file, you can assign components to that Placement Region, which tells Quilter to place those parts within the region's boundary.

<figure><img src="/files/2xeu8PzExCILlMWIkeSt" alt=""><figcaption><p>Placement Regions appear as dotted lines in the board preview.</p></figcaption></figure>

<figure><img src="/files/dMrGMb3O08b4Je4ExqLf" alt=""><figcaption><p>Review and manually add / remove components associated to each placement region before submitting your layout job.</p></figcaption></figure>

### Why should I pre-place components?

There are a few reasons to pre-place components:

1. **Location-sensitive components**\
   Pre-placing a component mainly ensures that location-sensitive parts, such as mechanical components and connectors, are positioned correctly. <br>
2. **Unsupported physics constraints**\
   If Quilter doesn't yet support a physics constraint that requires precise or highly organized placement of components, you can manually pre-place individual components or groups to ensure they come out correctly. <br>
3. **"Saving your progress"**\
   When iterating with Quilter, you might find yourself liking parts of a layout candidate but not the entire design. After downloading a candidate, you can pick the elements you like, remove the rest, and resubmit to Quilter to save your progress and move closer to a fabrication-ready design.

### How to specify

#### As a preference

Quilter won't put a component in a placement region outside of that region, even if it blocks Quilter from finishing a layout job.&#x20;

#### As a requirement

Define a placement region by following these steps for your CAD tool:<br>

{% tabs %}
{% tab title="In Altium" %}
Quilter utilizes Altium's "[Rooms](https://www.altium.com/documentation/altium-designer/pcb-rooms?srsltid=AfmBOopok-8wYiEOu-I8Is33x2w8w9GmT9s60KumbmLIqzAMSkw2gBS4)" feature to define placement regions and associate components with those regions. &#x20;

To define a placement region for Quilter:

1. **Create a Room in Altium.**  \
   You can use any of the following methods:
   1. Select the required command from the **Design » Rooms** submenu, then either interactively define the room shape (if you selected a **Place** command) or automatically create the room (if you selected a **Create** command). &#x20;
   2. Add a new **Room Definition** design constraint, edit the new room constraint, and click the **Define** button to interactively define the shape of the polygonal room. &#x20;
   3. Create a room based on a selected closed outline formed by a set of tracks or arcs using the **Tools » Convert » Create Room from Selected Primitives** command. &#x20;
   4. Automatically create rooms during schematic to PCB design synchronization. Learn more about [automatically generated rooms](https://www.altium.com/documentation/altium-designer/pcb-rooms?srsltid=AfmBOopok-8wYiEOu-I8Is33x2w8w9GmT9s60KumbmLIqzAMSkw2gBS4#created_during_schematic_to_pcb_design_synchronization) (including how to disable them).<br>
2. **Save and upload your input file.**  \
   Quilter will automatically parse your input board file to extract the Rooms as placement regions and automatically associate components in that room with the corresponding placement region.<br>
3. **Review your input file.**  \
   After uploading, you can inspect your input file to ensure that Quilter generated the placement regions correctly. Placement regions will be highlighted as dotted lines in the board preview.<br>
4. **Review and approve associated components.**  \
   Components in the Room will be automatically associated with the corresponding placement region. You can add or remove components as you wish.<br>
5. **Submit your layout job.**  \
   Once you're done, submit your layout job, and Quilter handles the rest.
   {% endtab %}

{% tab title="In Cadence" %}
Quick tutorial video for creating rooms in Cadence:\
<https://www.loom.com/share/6852c997f6c04aada293a06e215b285c><br>

If you have problems using Cadence using Parallels on a Mac, it may help to move your project into a folder like C:/Demos/my\_demo rather than on the Desktop. The desktop folder is a network-shared folder between Parallels Windows and native Mac and this can cause issues.
{% endtab %}

{% tab title="In KiCAD" %}
Quilter utilizes KiCAD's "Rule Areas" feature to define placement regions. Components must be manually associated with placement regions after being imported into Quilter.<br>

To define a placement region for Quilter:

1. **Create a Rule Area in KiCAD**\
   Use the corresponding icon on the right-hand menu:
   1. It must be associated with the top or bottom layer (usually `F.Cu` or  ).
   2. Define it as a "Keepout" and give it a recognizable name.
   3. <mark style="background-color:red;">Deselect all keepout items.</mark> This indicates to Quilter that it is a placement region and not a keepout (which Quilter also supports).\
      \ <img src="/files/fiWDDKVvCM8rQADdrmrc" alt="" data-size="original"><br>
2. **Save and upload your input file**\
   Quilter will automatically parse your input board file to extract the Rooms as placement regions and automatically associate components in that room with the corresponding placement region.<br>
3. **Review your input file** \
   After uploading, you can inspect your input file to ensure that Quilter generated the placement regions correctly. Placement regions will be highlighted as dotted lines in the board preview.<br>
4. **Associate components with the placement region**\
   Manually add components to the placement region using their reference designator.<br>
5. **Submit your layout job**\
   Once you're done, submit your layout job, and Quilter handles the rest.
   {% endtab %}
   {% endtabs %}


# Single-sided placement

Instructions for managing single-sided placement in Quilter, including automatic exploration, forcing double-sided layouts, and specifying single-sided constraints.

### Overview

When exploring placement solutions, Quilter will automatically flip components between the top and bottom layers unless they are specifically associated with a placement region on that layer.

For every layout job, **Quilter automatically tries to create some single-sided layout candidates** if it finds a valid placement solution that uses only one side.&#x20;

### How to specify

#### As a preference

Quilter allows for preferential filtering by single-sided placement. To do this, go to the design parameters page and check the "Show single-sided layouts only" option. This will apply a filter during candidate review that you can remove if we don't generate any single-sided candidates.

#### As a requirement

Quilter will automatically try single-sided candidates first and only switch to double-sided placements if it can't find a valid solution. \
To make Quilter only explore single-sided placements, create [Placement regions](/design-parameters/placement-regions) that include all components and link them to the top layer of your PCB.


# Pre-routed traces

Instructions for managing pre-routed traces in Quilter, including reasons to pre-route, handling during layout, and specifying locked routing paths.

### Overview

Quilter considers all traces and vias within the board boundary at the time of file upload to be "pre-placed".&#x20;

**As a foundational rule, Quilter does not alter the path or position of pre-placed traces and vias.** Quilter will not automatically delete unconnected or orphaned trace segments, so be sure to remove them from your input file before submission.&#x20;

During compilation, Quilter will strive to place and route all components that are not already routed. If a pre-routed trace segment is incomplete, Quilter will attempt to finish it during routing.

{% hint style="warning" %}
**Pre-routed traces on internal layers**\
If your input file includes pre-placed copper traces or pours on internal layers and you have *not* selected to preserve the stack-up in your input file, Quilter will delete them and generate new ones for each candidate and layer stack it explores.
{% endhint %}

### Why should I pre-route traces?

There are a couple of reasons to pre-route components:<br>

1. **Unsupported physics constraints**\
   If Quilter doesn't yet support a physics constraint that needs sensitive or highly organized signal routing, you can manually pre-place and route individual components to ensure they work correctly. <br>
2. **"Saving your progress"**\
   When iterating with Quilter, you might find that you like certain parts of a layout candidate, but not the overall design. Once you've downloaded a candidate, you can choose to keep the routing and placements you like, remove the rest, and resubmit to Quilter to save your progress toward a fabrication-ready design.

### How to specify

Locking the path of a copper trace is easy – just pre-route it within the board outline and upload your input file to Quilter.&#x20;


# Preserved pours

### Overview

Unlike [Pre-routed traces](/design-parameters/pre-routed-traces) Quilter **does not** automatically preserve copper pours that are present within the board boundary at the time of file upload.

**Instead, Quilter only preserves copper pours that are represented in the "preserved pours" table during Circuit Comprehension.** All other pours on internal or external copper layers are deleted and regenerated by Quilter.

Preserved pours can be added manually during job setup. In the near future, Quilter will automatically preserve pours that are marked as "locked" in the input file.

{% hint style="warning" %}
If you identify Preserved Pours on internal layers but choose not to preserve the stack-up when setting up your layout job, Quilter will still delete them and generate new internal layers for each layer stack and layout candidate it explores.
{% endhint %}

### Why should I use preserved pours?

There are a number of reasons to preserve copper pours:<br>

1. **"Saving your progress".** If you are iterating with Quilter, you may find that you like elements of a layout candidate, but not the whole design. After downloading a candidate, you can choose to preserve the routing/placements you like, unplace and unroute the rest, and resubmit to Quilter to "save your progress" towards a fabrication-worthy design.<br>
2. **Define advanced power planes for custom stack-ups.** Preserved pours will allow you to generate custom stackups that include custom and split power planes that supplement or replace the power planes recommended by Quilter.

### How to specify

To specify a preserved pour, follow these instructions:

1. **Create the pour.** Create or identify an existing pour in your input board file that you wish to preserve during compilation.
   1. If using KiCAD - make sure that the pour has a name.&#x20;
2. **Upload your input file.** Save and upload the input file to Quilter. You can confirm that the pour was parsed correctly by toggling the "Pours" layer in the board preview.
3. &#x20;**Add your "Preserved Pour".** Add your preserved pour by name to the "Preserved Pours" comprehension when setting up your layout job.


# Keepouts

Summary of using Keepouts in Quilter to restrict placement and routing areas, including common uses and how to specify them in your CAD tool.

### Overview

Quilter integrates directly with keepouts defined in your CAD tool, so you can control where traces, vias, components, and pours are allowed.&#x20;

That's pretty much it – just add a keepout to your board, and we'll steer clear of it!

### Why should I use keepouts?

Keepouts can help Quilter define the desired boundaries for design activity. Some common reasons to use keepouts include:

1. **Reserving space for mechanical features**, such as mounting holes, connectors, and heat sinks, where traces or components shouldn't go.
2. **Protecting sensitive areas**, like RF zones, from routing that could affect signal integrity.
3. **Enforcing design intent**, such as keeping parts out of high-heat zones or away from noisy power areas.

### How to specify

Uploading a keepout to Quilter for layout candidate generation is easy. Just define it in your CAD tool as you normally would and save it along with your other design files when setting up a new layout job.


# Net Widths by Layer

Explanation of Quilter’s Net Width constraint, detailing careful usage guidelines, potential conflicts with automatic constraints, and instructions for specifying custom widths.

### Net Widths by Layer

In general, Quilter's development philosophy is to understand your design at the [Physics Constraints](/physics-constraints/overview) level so that design parameters, such as Net Widths, can be independently managed on a constraint-by-constraint basis by Quilter, as opposed to using traditional design rules that can be overly conservative and cumbersome to define.

That said, Quilter supports a "Net Widths" constraint that can be used to specify specific trace widths for individual nets and net classes within your design.&#x20;

If you want to assert custom [Fabricator constraints](/using-quilter/fabricator-constraints) for your design, we recommend waiting until our support for custom stack-ups and design rules is complete.

{% hint style="warning" %}
**Use Net Widths Carefully**\
We don't recommend using the "Net Widths" constraint for global enforcement of fabrication rules. Net widths can "collide" with other physics constraints that automatically manage net widths and spacing, including [Power Nets](/physics-constraints/power-nets). We recommend using this constraint sparingly.
{% endhint %}

### How to specify

To specify a preserved pour, add the specific net or net class to the "Net Widths" constraint during Circuit Comprehension by clicking the `Add`, `Add multiple`, or `Add by netclass` buttons beneath the table.

<figure><img src="/files/94Ph82f0gGQxFHaa9ycu" alt=""><figcaption><p>Add by net</p></figcaption></figure>

<figure><img src="/files/jTsHbO6Mw1qp035LL8vE" alt=""><figcaption><p>Add by net class</p></figcaption></figure>


# Overview

Overview of Quilter’s Candidate Review page, highlighting tools for exploring, inspecting, and iterating on layout candidates generated by Quilter.

Quilter will start presenting candidates for your review as soon as the first one is complete.&#x20;

Depending on the setup of your layout job, Quilter may return up to 6 candidates that were part of its exploration of your design.&#x20;

Quilter offers various tools to help you easily explore, select, and refine the layout candidates it generates.

### Finding the right candidate

<table><thead><tr><th width="173.37109375">Topic</th><th>Description</th></tr></thead><tbody><tr><td><a data-mention href="/pages/sewZKbPlw2MBH1jmjKWj">/pages/sewZKbPlw2MBH1jmjKWj</a></td><td>Job details provide an overview of the key information for the layout job request and its generated results.</td></tr><tr><td><a data-mention href="/pages/KlfAFXD8YVuW9Uc6E3KD">/pages/KlfAFXD8YVuW9Uc6E3KD</a></td><td>Candidate details capture essential information about the candidate that can be utilized to sort and filter your solution space.</td></tr></tbody></table>

### Inspecting candidates

<table><thead><tr><th width="173.5">Topic</th><th>Description</th></tr></thead><tbody><tr><td><a data-mention href="/pages/64CusstmdLbAVTzL0oiU">/pages/64CusstmdLbAVTzL0oiU</a></td><td>Quilter's <a data-mention href="/pages/CWMdylEJnQkGi7wLROTd">/pages/CWMdylEJnQkGi7wLROTd</a> help you understand the physics constraints we were able and unable to meet.</td></tr></tbody></table>

### Offline review & iteration

<table><thead><tr><th width="173.5">Topic</th><th>Description</th></tr></thead><tbody><tr><td><a data-mention href="/pages/E5SgLPBfGIvdVSpCkdOv">/pages/E5SgLPBfGIvdVSpCkdOv</a></td><td>Continue candidate review offline by downloading your preferred candidates in their original file formats.</td></tr><tr><td><a data-mention href="/pages/QWL3m6I70joJgcispRXS">/pages/QWL3m6I70joJgcispRXS</a></td><td>Utilize Quilter's iterative capabilities to refine your design further across multiple layout jobs.</td></tr></tbody></table>


# Job details

Summary of Quilter’s Job Details, providing high-level metadata about submitted input files, configured parameters, and board previews for layout jobs.

### Overview

Job details give you a high-level overview of the inputs and preferences you set when you submitted your layout job.&#x20;

This info helps you understand how complex the job is that you're asking Quilter to handle (see [What Quilter does well](/about-quilter/what-quilter-does-well)), as well as the specific parameters used to generate candidates.

### Job details modal

<figure><img src="/files/ewFLbwTMrwLhYFFe40lF" alt=""><figcaption></figcaption></figure>

Press the "Details" button in the top right corner of the job details header to view the job details used to generate your layout job.&#x20;

Here's what you'll find in the job details modal:

* An overview of the job details
* A summary of the input files used, along with a button to **download them** for a submitted job
* A summary of the [Physics Constraints](/physics-constraints/overview)associated with your layout job
* A summary of the [Design Parameters](/design-parameters/overview)specified for your layout job
* A board preview of the input files used to create your layout job

### Available metadata

<figure><img src="/files/ciwJf9nfgQUovz9CP6sa" alt=""><figcaption><p>Job details summarized after file upload when configuring a new layout job.</p></figcaption></figure>

<table><thead><tr><th width="185.87109375">Field</th><th>Description</th></tr></thead><tbody><tr><td>Job name</td><td>The name you assign to your layout job. If you wish, Quilter will automatically generate a default name from your input files.</td></tr><tr><td>Board dimensions</td><td>The dimensions of your board, in centimeters.</td></tr><tr><td>Components</td><td>The number of components detected within your design.</td></tr><tr><td>Components to place</td><td>The number of unplaced components that Quilter will attempt to place within your design.</td></tr><tr><td>Pins</td><td>The number of component pins detected within your design.</td></tr><tr><td>Pins to route</td><td>The number of unrouted component pins that Quilter will attempt to route within your design.<br><br>All layout jobs submitted to Quilter must have > 0 pins to route.</td></tr><tr><td>Pin density</td><td>A metric that identifies the % routable surface area of the board, specified as:<br><br>Pin density (%) = (Component Pin Area) / (Total Board Surface Area) * 100% </td></tr></tbody></table>


# Candidate details

Summary of Quilter’s Candidate Details, highlighting metadata used to sort, filter, and select layout candidates based on specific design criteria.

### Overview

Candidate details capture important metadata about your design that can be used to sort, filter, and identify layout candidates that best meet your design criteria.

<figure><img src="/files/Em9VsywVxFQIDvTr7AEj" alt=""><figcaption></figcaption></figure>

### Available metadata

Quilter presents the following candidate metadata for review, some of which can be used to create filters on the candidate review page.

<table><thead><tr><th width="156.38671875">Field</th><th width="437.25">Description</th></tr></thead><tbody><tr><td>Candidate name</td><td>Idenfities the candidate number for easy identification</td></tr><tr><td>Routing completion</td><td>Identifies the % of pins to route that were successfully completed within the design.</td></tr><tr><td>DRC error count</td><td>Identifies the number of Quilter-generated DRC violations. Quilter currently prevents any candidate with DRC errors from being surfaced to Candidate Review.</td></tr><tr><td>Single-sided</td><td>Identifies whether the candidate uses single- or double-sided placement.</td></tr><tr><td>Layer count</td><td>Identifies the number of layers used in the design.</td></tr><tr><td>Minimum trace width</td><td>Identifies the minimum trace width used in the design. <br><br>This figure identifies the <em>actual</em> minimum trace width in the design (not the fabrication rules), which may include narrower widths resulting from neck-downs.</td></tr><tr><td>Minimum trace clearance</td><td>Identifies the minimum trace clearance used in the design.</td></tr><tr><td>Minimum via diameter</td><td>Identifies the minimum via diameter used in the design.</td></tr><tr><td>Minimum drill diameter</td><td>Identifies the minimum drill diameter used in the design.</td></tr><tr><td>Via count</td><td>Identifies the number of individual vias used in the design.</td></tr></tbody></table>


# Filtering

Overview of Quilter’s filtering tools, describing automatic filter application, real-time candidate updates, and options to reset filters for candidate exploration.

### Overview

Quilter provides straightforward filters that let you quickly pinpoint candidates that meet your design criteria.&#x20;

When you submit your layout job, if you include Design Parameter preferences (see [Select your stackup](/using-quilter/select-your-stackup)), they'll be automatically used as filters to help you narrow down to the candidates that match your preferences.

<figure><img src="/files/L8GaipP1UpY41vnxdIrT" alt=""><figcaption></figcaption></figure>

### Using filters

Here are a few notes on using filters:

* Updating filters changes the layout candidates visible in your candidate list in real time.&#x20;
* You can click the `Reset Filters` button to clear all filters and view all candidates explored by Quilter throughout the layout job.&#x20;
* The `Show 100% routed candidates only` filter is automatically applied to all jobs, and you can manually clear it at any time to see <100% routed layout candidates.

### Supported filters

<table><thead><tr><th width="190.04296875">Filter</th><th width="147.70703125">Type</th><th>Behavior</th></tr></thead><tbody><tr><td>Show 100% routed candidates only</td><td>Toggle</td><td>Activating this filter hides incomplete (&#x3C;100% routed) candidates</td></tr><tr><td>Single-sided</td><td>Checkbox</td><td>Activating this filter shows only single-sided layout candidates</td></tr><tr><td>Trace Width (min)</td><td>Single select</td><td>This filter shows candidates with minimum trace widths that <strong>match or exceed</strong> the specified value</td></tr><tr><td>Trace Clearance (min)</td><td>Single select</td><td>This filter shows candidates with minimum trace clearance that <strong>match or exceed</strong> the specified value</td></tr><tr><td>Layers</td><td>Multi-select</td><td>This filter shows candidates whose layer count match the specified selection(s)</td></tr><tr><td>Fabricators</td><td>Multi-select</td><td>This filter shows candidates whose stack-up is designed for fabrication by the specified manufacturer(s)</td></tr></tbody></table>


# Sorting

Overview of Quilter’s candidate sorting, detailing default sorting criteria for routing completion, fabrication rules, layer count, and future sorting enhancements based on PRC results.

### Overview

The Quilter's recommendation (sorting) algorithm aims to assist users in quickly identifying the best boards that Quilter explored during the layout job.&#x20;

The sorting and filtering functions work together to help you efficiently find the best board that aligns with your design preferences.

Our sorting algorithms consider the following attributes for each layout candidate:

* **Completeness**, including % routing completion and # DRC violations
* **Fabrication rules,** including minimum trace width/spacing, minimum drill/via size, and minimum edge clearance
* **PRC performance,** which references PRC results for both priority and other physics constraints. The following physics constraints are considered "Priority":
  * [Power Nets](/physics-constraints/power-nets)
  * [Differential Pairs](/physics-constraints/differential-pairs)
  * [Single-ended Impedance Control](/physics-constraints/single-ended-impedance-control)

### Sort types

#### Recommended

Quilter's "Recommended" sort aims to help identify the most conservative stack-up and fabrication rules that maximize priority PRC completion candidates:

1. **Highest routing completion**
   1. `min` Number of DRC violations, `ASC`
   2. `max` Routing completion, `DESC`
2. **Priority PRC completion**
   1. `max` Passing Priority PRCs, `DESC`
3. **Most conservative fabrication rules**
   1. `max` Minimum trace width, `DESC`
   2. `max` Minimum trace clearance, `DESC`
   3. `max` Minimum drill size, `DESC`
   4. `max` Minimum via size, `DESC`
4. **Fewest layers**
   1. `min` Layer count, `ASC`
5. **Other PRC completion**
   1. `max` Passing Other PRCs, `DESC`
6. **Most efficient routing**
   1. `min` Shortest traces, `ASC`

#### Best PRCs

Quilter's "Best PRCs" sort prioritizes PRC completion over all other considerations except completion:

1. **Highest routing completion**
   1. `min` Number of DRC violations, `ASC`
   2. `max` Routing completion, `DESC`
2. **PRC completion**
   1. `max` Passing Priority PRCs, `DESC`
   2. `max` Passing Other PRCs, `DESC`
3. **Most conservative fabrication rules**
   1. `max` Minimum trace width, `DESC`
   2. `max` Minimum trace clearance, `DESC`
   3. `max` Minimum drill size, `DESC`
   4. `max` Minimum via size, `DESC`
4. **Fewest layers**
   1. `min` Layer count, `ASC`
5. **Most efficient routing**
   1. `min` Shortest traces, `ASC`

#### Easiest to Fab

Quilter's "Easiest to Fab" sort prioritizes conservative fabrication rules over all other considerations except completion:

1. **Highest routing completion**
   1. `min` Number of DRC violations, `ASC`
   2. `max` Routing completion, `DESC`
2. **Most conservative fabrication rules**
   1. `max` Minimum trace width, `DESC`
   2. `max` Minimum trace clearance, `DESC`
   3. `max` Minimum drill size, `DESC`
   4. `max` Minimum via size, `DESC`
3. **Fewest layers**
   1. `min` Layer count, `ASC`
4. **PRC completion**
   1. `max` Passing Priority PRCs, `DESC`
   2. `max` Passing Other PRCs, `DESC`
5. **Most efficient routing**
   1. `min` Shortest traces, `ASC`

#### Fewest Layers

Quilter's "Fewest Layers" sort prioritizes low layer counts over all other considerations except completion:

1. **Highest routing completion**
   1. `min` Number of DRC violations, `ASC`
   2. `max` Routing completion, `DESC`
2. **Fewest layers**
   1. `min` Layer count, `ASC`
3. **Most conservative fabrication rules**
   1. `max` Minimum trace width, `DESC`
   2. `max` Minimum trace clearance, `DESC`
   3. `max` Minimum drill size, `DESC`
   4. `max` Minimum via size, `DESC`
4. **PRC completion**
   1. `max` Passing Priority PRCs, `DESC`
   2. `max` Passing Other PRCs, `DESC`
5. **Most efficient routing**
   1. `min` Shortest traces, `ASC`


# Review phases


# Detail view

Overview of Quilter’s board detail viewer, describing controls for inspecting board layers, toggling visibility of objects by layer or globally, and navigating layout details.

### Overview

Quilter's "Detail View" lets you take a closer look at specific board layers and object classes within your layout candidate.&#x20;

You can access the full-screen "Detail View" by clicking the "Detail View" button in the top-right corner of the board preview component.

<figure><img src="/files/lga8jf64V6Mxste65UQt" alt=""><figcaption></figcaption></figure>

### Supported controls

Quilter's board viewer includes the following controls to help with inspecting and reviewing Quilter-generated layout candidates:

<table><thead><tr><th width="158.82421875">Control</th><th>Description</th></tr></thead><tbody><tr><td>2D mode</td><td>The default viewing style displays your design in a locked birds-eye view without three-dimensional features.</td></tr><tr><td>3D mode</td><td>Displays a 3D perspective of your board with a materials-based visual theme. Enables free rotation.</td></tr><tr><td>Flip icon</td><td>Quickly flip your board from front to back</td></tr><tr><td>Quick find</td><td>Locate and switch to a specific camera angle for a particular component or pin within your design. </td></tr></tbody></table>

### Layer/object navigation

Quilter's tag tree picker provides access to all board object classes through two different organizational views:<br>

1. **Control object visibility by layer**\
   The first set of controls lets you toggle the visibility of all objects on a specific layer or expand the nested tree structure to toggle the visibility of individual objects on that layer. These toggles are always available, even if there are no objects on that layer – for example, if there are no pours on `LAYER_1`.

   \
   Layer-level toggles are helpful for inspecting individual layers of your PCB at a time.<br>
2. **Control global object visibility**\
   The second set of controls lets you toggle the global visibility of specific object classes across all layers. These toggles are always available, even if there are no instances of that object in your design – for example, if there are no placement regions defined for your layout job.\
   \
   Global-level toggles are useful for inspecting trace paths that span multiple layers of your board.


# Reviewing PRCs

Overview of Quilter’s PRC reports, detailing how to interpret results grouped by constraint types, view passing and failing checks, and understand individual physics rule evaluations.

### Overview

Every layout job comes with a [PRC report](/physics-rule-checks-prcs/overview) that summarizes the results of physics unit tests Quilter runs for each of the defined layouts in your job.&#x20;

The goal of PRCs is to help assess whether the layout candidate generated by Quilter is likely to perform as expected.

### Interpreting PRC results

#### How PRCs are organized

Quilter's PRC reports are generated for every candidate Quilter considers.&#x20;

The PRC results are organized by the parent constraint type they support – for example, bypass capacitors, differential pairs, and so on. You can expand or collapse the individual results for each constraint group by clicking the header for that constraint type.

A summary of the aggregated PRC results is also available on the right side of the constraint group header. You can filter the PRC checks shown to view all of them (the default) or only the ones that failed to pass.&#x20;

#### Reading individual results

<figure><img src="/files/wrYHENBbd3bSMY2cuzJN" alt=""><figcaption></figcaption></figure>

Along with grouping by constraint type, PRC results are also organized by the physics constraint they support. You can see information about the associated constraint on the left side.

PRCs that pass are shown in <mark style="background-color:green;">**green,**</mark> while those that fail are displayed in <mark style="background-color:red;">**red**</mark>**.**

Each PRC includes:

* The name of the check that was run
* The check's result
* The tolerances that indicate a passing result for that check

A complete list of PRCs, including the physics justification and assessment methodology, can be found in [Physics Rule Checks (PRCs)](/physics-rule-checks-prcs/overview).


# Edit & iterate


# Job Actions

Summary of Quilter’s Job Actions, describing available actions such as duplication for iteration, modification of constraints, and adjustments to design parameters.

### Overview

Quilter offers various job actions to help you efficiently iterate and organize your layout jobs. You can access these job actions in two locations: the Layout Jobs Overview page and the Candidate Details header.

<figure><img src="/files/8AGoO4CvB2EXZX7cNmPu" alt=""><figcaption><p>Access job actions from the layout jobs home page.</p></figcaption></figure>

<figure><img src="/files/oMkbC9npavxLOjmCbKtH" alt=""><figcaption><p>Access job actions from the candidate details header.</p></figcaption></figure>

### Supported job actions

<table><thead><tr><th width="162.62109375">Job Action</th><th>Description</th></tr></thead><tbody><tr><td>Details</td><td>View details about the input files, physics constraints, and design parameters associated to your layout job</td></tr><tr><td>Rename</td><td>Update the name of your layout job</td></tr><tr><td>Delete</td><td>Delete this layout job from your Quilter account. <strong>Deleted layout jobs cannot be recovered.</strong></td></tr><tr><td>Duplicate</td><td>Copies the input files and physics constraints defined for your existing layout job to a new draft job.</td></tr></tbody></table>

{% hint style="success" %}
**Using "Duplicate" for iteration.**\
Our "duplicate" action simplifies running new versions of the same layout job with slight changes to the input files or physics constraints.\
\
Use the "duplicate" feature to re-run your layout job with:

* **Updated constraints**, such as a corrected bypass capacitor connection
* **Different design parameters**, like corrected connector placements or a new placement area
  {% endhint %}


# Downloading candidates

Overview of downloading Quilter-generated layout candidates, including native file formats for offline review, and tracking downloaded jobs.

### Overview

Once you've reviewed a layout candidate, you can download it for offline inspection. To download a candidate for offline review, click the "download" button at the bottom right of the candidate preview pane.&#x20;

Layout candidates are always returned in their original native file format, making it easy to inspect and review them offline. This way, you can:

* Run your own design rule checks (DRCs)
* Validate the design with simulation
* Send the design to colleagues for feedback and approval

<figure><img src="/files/HMTWNODoIebgMIIMcGQG" alt=""><figcaption><p>Click the button to download your layout candidate</p></figcaption></figure>


# Page 1


# Glossary


# User resources


