Overview
Explanation of how Quilter identifies, categorizes, and manages physics constraints during Circuit Comprehension, including automatic detection and manual specification.
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Explanation of how Quilter identifies, categorizes, and manages physics constraints during Circuit Comprehension, including automatic detection and manual specification.
Last updated
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During the Circuit Comprehension step, Quilter gathers key physics concerns from your design and converts them into various physics constraints.
Quilter tries to automatically identify as many constraints as possible by analyzing the board and schematic files you provide. It uses a range of features from these files, including object and net classes, component and net names, pin names, connections, and the relative position of components.
There are two types of constraints:
Routing Constraints impact the properties of traces and guarantee that key electrical characteristics stay within specified limits. Our current routing constraints are:
Placement Constraints help keep components tightly placed to reduce trace length. Our current placement constraints are:
All nets without constraints are routed as generic signals Quilter treats all signals that aren't represented in Circuit Comprehension as generic, low-speed digital signals. If your physics constraints aren't yet supported by Quilter, we recommend pre-placing or pre-routing them before submission.
Every constraint has its own set of rules for detection and assignment. Knowing these rules can help you resolve edge cases or unexpected behavior. By using specific netclasses, patterns, and naming conventions, Quilter can identify your constraints. You'll find more details on this in the documentation that follows.
Quilter also lets you manually enter any constraints you need to include.
Position oscillators close to their drivers to minimize phase noise and startup issues.
Automatically detected
Ensure tight ground return loops for input and output paths to reduce EMI and voltage ripple.
Automatically detected
Ensure a stable, low-impedance signal path for power pins.
Automatically detected
Design high-current nets as traces with a specified width or as copper pours.
Automatically detected
Generate differential pairs with controlled lengths and impedances for high-speed digital signals.
Automatically detected
Impedance-controlled nets for RF nets or other fast, long, or sensitive traces.
Manual
Length matching for timing-sensitive interfaces such as DDR memory
Manual